HYB18T512160AF-3 QIMONDA [Qimonda AG], HYB18T512160AF-3 Datasheet - Page 41

• Manufacturer Part Number: HYB18T512160AF-3
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

7.2
This chapter contains the AC timing parameters.
Rev. 1.71, 2007-01
03062006-CPCN-4867
Parameter
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time
DQ and DM input pulse width for each input
DQS output access time from CK / CK
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated DQ signals
DQS latching rising transition to associated clock
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
Data-out high-impedance time from CK / CK
Address and control input hold time
Control & address input pulse width for each input
Address and control input setup time
DQ low impedance time from CK/CK
DQS/DQS low-impedance time from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
DQ/DQS output hold time from DQS
DQ hold skew factor
AC Timing Parameters
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH.AVG
CK.AVG
CKE
CL.AVG
DAL
DELAY
DH.BASE
DIPW
DQSCK
DQSH
DQSL
DQSQ
DQSS
DS.BASE
DSH
DSS
HP
HZ
IH.BASE
IPW
IS.BASE
LZ.DQ
LZ.DQS
MOD
MRD
OIT
QH
QHS
41
DDR2–667
–450
2
0.48
3000
3
0.48
WR +
t
t
175
0.35
–400
0.35
0.35
—
– 0.25
100
0.2
0.2
Min (
t
—
275
0.6
200
2 x
t
0
2
0
t
—
Min.
IS
IH
CL.ABS
AC.MIN
HP
+
–
t
AC.MIN
t
t
CK .AVG
t
CH.ABS
)
QHS
t
nRP
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
,
+
+450
—
0.52
8000
—
0.52
––
—
+400
—
—
––
—
—
—
—
—
12
—
12
Max.
—
––
240
+ 0.25
__
t
t
t
—
340
AC.MAX
AC.MAX
AC.MAX
512-Mbit DDR2 SDRAM
Unit
ps
nCK
t
ps
nCK
t
nCK
ns
ps
t
ps
t
t
ps
t
ps
t
t
ps
ps
ps
t
ps
ps
ps
ns
nCK
ns
ps
ps
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
CK.AVG
Internet Data Sheet
TABLE 40
Note
8)
—
9)10)
—
11)
9)10)
12)13)
—
18)19)14)
—
8)
—
—
15)
16)
17)18)19)
16)
16)
20)
8)21)
24)22)
—
23)24)
8)21)
8)21)
30)
—
30)
25)
26)
1)2)3)4)5)6)7)