NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 80

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

Timings
9.3.2
Figure 23. Multiple Block Write command timing diagram
80/116
DAT0
DAT1-7
CMD
Card
Rsp.
Z
Z
E Z
Z
Z
Multiple Block Write
In Multiple Block Write mode, the device is sent a continuous flow of data blocks following
the initial host write command. The data flow is terminated by a STOP_TRANSMISSION
command (CMD12).
See
device busy flag.
The STOP_TRANSMISSION command works in the same way as for Read operations. The
device considers a data block as successfully received and ready for programming only if
the CRC data of the block was validated and the CRC status token sent back to the host.
Figure 25
bit of the host command is followed, on the data line, with one more data bit, an end bit and
two Z clock for switching the bus direction. In this case the received data block is considered
incomplete and will not be programmed.
In an open-ended Multiple Block Write case the busy flag between the data blocks should
be considered as buffer busy flag. As long as there is no free data buffer available the device
should indicate this by pulling down the Dat0 line. The device stops pulling down DAT0 as
soon as at least one receive buffer for the defined data transfer block length becomes free.
After the device receives the stop command (CMD12), the following busy indication should
be considered as programming busy and being directly related to the Programming state. As
soon as the device completes the programming, it stops pulling down the Dat0 line.
In pre-defined Multiple Block Write case the busy flag between the data blocks should be
considered as buffer busy flag similar to the open-ended multiple block case. After the
device receives the last data block the following busy indication should be considered as
programming busy and being directly related to the Programming state. The meaning of
busy flag (from buffer busy to programming busy) changes at the same time with the state
change (from rcv to prg). The busy flag remains “low” all the time during the process and is
not released by the device between the state change from rcv to prg. As soon as the device
completes the programming, it stops pulling down the Dat0 line.
See
stopping the data transmission during an active data transfer, while
describe scenarios of STOP_TRANSMISSION command received between data blocks
transmission. In
the device is idle. Unprogrammed data blocks remain in the input buffers and will be
programmed as soon as the STOP_TRANSMISSION command is received and the device
activates the busy flag.
N
Z P
P*P S
P*P S
WR
Figure 23
Figure 24
* * * * * * * * * * * * * * * * * P
Write Data
is an example of an interrupted attempt to transmit the CRC status block. The end
Data+CRC
Data+CRC
for a description of Multiple Block Write timing diagrams with and without
and
Figure 26
Figure 25
E
E
Z
Z
Z
Z
the device is busy programming the last block while in
S
X
CRC
Status
Status
* * * * *
show examples of timing diagrams corresponding to host
P
E Z
X Z
P
N
P
P*P
P*P
WR
P
S
S
* * * * * * * * * * * * * * * * *
Write Data
Data+CRC
Data+CRC
NAND08GAH0A, NAND16GAH0D
E
E
Z
Z
Z
Z
S
X
CRC
Status
Status
Figure 26
* * * * * * * *
P
P P
E
S
Busy
P P
L*L
and
X
P
E
Figure 27
Figure 27
P
Z
Z
N
AI13601
P
P*P
P*P
WR
P