NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 78

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

Timings
9.2
9.2.1
Figure 19. Single Block Read command timing diagram
9.2.2
Figure 20. Multiple Block Read command timing diagram
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DAT
CMD
S T
Z Z
Host Command
Z
Data Read timings
Single Block Read
The host selects one device for data read operation by issuing a CMD7 command. It then
sends a CMD16 command to set the valid block length for block oriented data transfer.
Figure 19
with a single block read command (CMD17) which specifies the start address in the
argument field. The response is sent on the CMD line as usual. Data transmission starts
N
check bits are suffixed to allow the host to check for transmission errors.
Multiple Block Read
In Multiple Block Read mode, the device sends a continuous flow of data blocks following
the initial host read command. The data flow is terminated by a STOP_TRANSMISSION
command (CMD12).
Figure 20
STOP_TRANSMISSION command. The data transmission stops two clock cycles after the
end bit of the STOP_TRANSMISSION command.
Content
* * * *
AC
DAT
CMD
clock cycles after the end bit of the host command. After the last data bit, the CRC
Z Z
shows the timing diagram for a Single Block Read operation. The sequence starts
describes the timing of the data blocks and
CRC
S T
Z Z
Z
Host Command
Z
E
Z
Content
Z
Z
* * * *
Z
Z
N
Cycles
CR
P
P
N
Z Z
AC
* * * * * * * *
*
CRC
P
Cycles
Z
S
E
Z
T
Z
Z
Card Response
Content
Z
Z
P S
N
Cycles
P
P
CR
N
* * *
D D
* * * * * * * * *
AC
Read Data
Cycles
CRC
P
D
S
* * *
E
T
Card Response
Z Z
*
Content
Figure 21
D
P S
NAND08GAH0A, NAND16GAH0D
E
P
Read Data
D D
P
P
N
P
* * * * * *
AC
CRC
D
P
the response to a
Cycles
AI04330
* * *
P P
E
P P
P S
Read Data
P
D
P
D D
P
AI04331
P
D
D
P