NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 77

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GAH0A, NAND16GAH0D
9.1.4
Figure 16. R1b response timing diagram
9.1.5
Figure 17. Last device response to Next Host command timing diagram
9.1.6
Figure 18. Command n end to CMD n+1 start timing diagram (all modes)
CMD
DAT0
DAT1-7
S T
Z Z
Z Z
R1b responses
Some commands, like CMD6, may assert the busy flag and send back a R1 response. If the
busy flag is asserted, this is done two clock cycles after the end bit of the command.
The DAT0 line is driven Low, DAT1-DAT7 lines are driven by the device though their values
are not relevant.
Last device response to Next Host command
After receiving the last device response, the host can start the next command transmission
after a minimum delay of is N
The timing diagram shown on
Last Host command to Next Host command
After the last command has been sent, the host can continue issuing the next command. A
minimum delay of N
If the device has not responded to the ALL_SEND_CID command after NID+1 clock
periods, the host can conclude that no devices are present on the bus.
See
CMD
CMD
Z Z
Z Z
Figure 18
Host Command
Content
S T
S T
Z Z
Z Z
Host Command
Z Z Z Z
Z Z Z Z
for a description of the timing diagram.
Content
Content
Response
CRC E Z
N
CC
ST
clock periods must be respected between the two commands.
Z Z S L
Z Z X
CRC E Z
CRC E Z
Z Z Z Z
CR
Figure 17
clock cycles.
* * * * * * * *
* * * * * * * *
N
N
* * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * *
CC
RC
* * * * * * * * * * * * * * * * *
Cycles
Cycles
applies to all host commands.
Card busy
Z S T
Z S T
Host Command
Host Command
Content
Content
Z
CRC E
CRC E
Z
AI13199
AI13198
Z
E
X
Z
Z
Z
AI13197
Z Z
Z
Z
Z
Z
Z
Z
Z
Z
Timings
77/116