NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 108

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

Serial peripheral interface (SPI) mode
10.9.2
Figure 44. Single Block Read timing diagram
Figure 45. STOP_TRANSMISSION between blocks in Multiple Block Read timing diagram
Figure 46. STOP_TRANSMISSION within a block in Multiple Block Read timing diagram
108/116
CS
DataIn
DataOut Z Z H H
CS
DataIn
DataOut Z Z H H
CS
DataIn
DataOut Z Z H H
H L L L
X H * * H
Data Read timings
The timing diagram for deselecting the device (by de-asserting CS after the last device
response) corresponds to a standard command-to-response timing diagram as illustrated in
Figure
During open-ended Multiple Block Read operations, the STOP_TRANSMISSION command
may be sent while the device is transmitting data to the host. In this case, the device stops
transmitting the data block within two clock cycles (the bits in the first byte may not all be set
to ‘1’) and returns the response message after a time measured in numbers of clock cycles
(N
Refer to
a description of Data Read timing diagrams.
H L L
X H * H
H L L
X H * H
CR
N
N
N
CS
).
CS
CS
41.
Table 71
H
H
H
Read Cmd
Read Cmd
H
* * * *
* * * *
Read Command H H H H H
* * * * * * *
for timing values and to
H H H H
H * H
H H H H
N
H * H
N
CR
CR
* * * * * * * * * * * * * * * * * * * * *
Card Resp
* * * * * * * * * * * * * * * * * * * * *
Card Resp
* * * * * * * * * * * * * * * * * * * * *
H * * H
N
* * * * * * * *
CR
* * * * * * * * * * *
H * H
H * H
N
N
Card Response
AC
AC
Figure
Data Block
Data Block
* * * * * * * * * * * *
44,
H
H H
Figure
H * * H
H * H
H * H
N
N
N
Stop Cmd
AC
AC
NAND08GAH0A, NAND16GAH0D
AC
H H
45,
Data Block
Data
Data Block
Stop Cmd
Figure
H H H
X X
H
N
H
46, and
CR
H H H H
L L L H H H H
H
H
H * H
H * H
N
* *
N
H H
H H
EC
CR
L L L L L
L L L L L
H
Card Resp
X X
H H
Card Resp
H H
Figure 47
Z Z
X X
H H
H H
Z
ai08375
ai08376
ai08377
for