NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 71

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GAH0A, NAND16GAH0D
8.4.7
8.4.8
8.4.9
8.4.10
8.4.11
CMD_SET
Contains the binary code of the command set that is currently active in the device. It is set to
‘0’ (Standard MMC) after power up and can be changed by a SWITCH command. Note that
while changing the command set with the switch command, values according to the
S_CMD_SET Register should be used, for example, bit0 set=0x01 for standard MMC.
CMD_SET_REV
Contains a binary number reflecting the revision of the currently active command set. For
standard MMC the command set it is:
Table 56.
This field, though in the modes segment of the EXT_CSD, is read only.
POWER_CLASS
This field contains the 4-bit value of the selected power class for the device. The power
classes are defined in
with the maximum power class it allows the device to use. The device uses this information
to, internally, manage the power budget and deliver an optimized performance.
This field is 0 after power-up or software reset.
Table 57.
HS_TIMING
This field is 0 after power-up, or software reset, thus selecting the backwards compatibility
interface timing for the device. If the host writes 1 to this field, the device changes its timing
to high speed interface timing (see
BUS_WIDTH
It is set to ‘0’ (1 bit data bus) after power-up and can be changed by a SWITCH command.
Table 58.
Standard MMC command set revisions
Power class code
Bus mode values
255-1
Value
Code
255-3
[7:4]
[3:0]
Bits
0
2
1
0
Table
57. The host should be responsible of properly writing this field
Table
9).
Reserved
v4.0
Reserved
Device power class code (See
Reserved
8 bit data bus
4 bit data bus
1 bit data bus
MMC revision
Description
Bus mode
Device registers
Table
47)
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