NAND08GAH0A NUMONYX [Numonyx B.V], NAND08GAH0A Datasheet - Page 43

• Manufacturer Part Number: NAND08GAH0A
• Manufacturer: NUMONYX [Numonyx B.V]

NAND08GAH0A, NAND16GAH0D
5.7
5.7.1
5.7.2
Error conditions
CRC and illegal commands
All commands are protected by CRC (Cyclic Redundancy Check) bits. If the addressed
device CRC check fails, the device does not respond and the command is not executed. The
device does not change its state, and the COM_CRC_ERROR bit is set in the Status
Register.
Similarly, if an illegal command has been received, the device will not respond or change its
state and will set the ILLEGAL_COMMAND error bit in the Status Register. Error conditions
are not shown in the state diagrams
complete state transition description.
There are different kinds of illegal commands:
●
●
●
Read, Write and Erase timeout conditions
The times after which a timeout condition for read/write/erase operations occurs are 10
times longer than the typical access/program times for these operations. A device will
complete the command within this time, or give up and return an error message. If the host
does not get a response within the defined timeout it should assume the device is not going
to respond and reset the device.
Table 16
Table 16.
1. See
Forced Erase
Read Access
Block Write
Erase time
maximum clock frequency.
Time
Commands which belong to classes not supported by the device (e.g. write commands
in read only devices)
Commands not allowed in the current state (e.g. CMD2 in Transfer state)
Undefined commands (e.g. CMD44).
time
time
time
Section 8.3: Card specific data register (CSD)
gives the formulae required to calculate typical access and program times.
Formulae to calculate typical access and program times
cycles
cycles
cycles
clock
clock
clock
Unit
min
Number of Erase groups * Block Write
(Read Access time * R2W_FACTOR)
(Figure 10
(TAAC + NSAC)
Formula
time
3
for the definition of the parameters used to calculate the
and
High speed MultiMediaCard operation
Figure
12). Refer to
These parameters define the
typical delay between the
end bit of the Read
command and the start bit of
the Data Block.
This applies to all
Write/Erase commands
This gives an approximate
value
Duration of the Forced Erase
operation using CMD42
command
Table 27
Description
(1)
for a
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