M45PE10-VMN6 STMICROELECTRONICS [STMicroelectronics], M45PE10-VMN6 Datasheet - Page 22

• Manufacturer Part Number: M45PE10-VMN6
• Description: 1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M45PE10
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V
correct value:
–
–
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while V
On Reset (POR) threshold value, V
tions are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE) and Sector Erase (SE) instruc-
tions until a time delay of t
the moment that V
old. However, the correct operation of the device
is not guaranteed if, by this time, V
V
should be sent until the later of:
–
Figure 19. Power-up Timing
22/34
CC
V
delay of t
V
t
(min). No Write, Program or Erase instructions
PUW
V CC (max)
V CC (min)
CC
SS
(min) at Power-up, and then for a further
at Power-down
after V
V WI
V CC
VSL
CC
Reset State
Device
of the
CC
passed the V
Program, Erase and Write Commands are Rejected by the Device
rises above the V
CC
CC
Chip Selection Not Allowed
) until V
PUW
is less than the Power
has elapsed after
WI
CC
CC
threshold
WI
is still below
reaches the
– all opera-
WI
thresh-
tPUW
tVSL
–
These values are specified in
If the delay, t
above V
READ instructions even if the t
fully elapsed.
As an extra protection, the Reset (Reset) signal
can be driven Low for the whole duration of the
Power-up and Power-down phases.
At Power-up, the device is in the following state:
–
–
Normal precautions must be taken for supply rail
decoupling, to stabilize the V
vice in a system should have the V
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V
ing voltage, to below the Power On Reset (POR)
threshold value, V
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Read Access allowed
t
V
The device is in the Standby Power mode (not
the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
VSL
CC
(min) level
after wrap roundV
CC
(min), the device can be selected for
VSL
, has elapsed, after V
WI
, all operations are disabled
Device fully
accessible
CC
CC
drops from the operat-
CC
passed the
Table
PUW
time
supply. Each de-
delay is not yet
CC
6..
CC
AI04009C
rail decou-
has risen