M45PE10-VMN6 STMICROELECTRONICS [STMicroelectronics], M45PE10-VMN6 Datasheet - Page 10

• Manufacturer Part Number: M45PE10-VMN6
• Description: 1 Mbit, Low Voltage, Page-Erasable Serial Flash Memory With Byte-Alterability and a 25 MHz SPI Bus Interface
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M45PE10
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read) or Read
Status Register (RDSR) instruction, the shifted-in
instruction sequence is followed by a data-out se-
Table 4. Instruction Set
10/34
FAST_READ Read Data Bytes at Higher Speed
Instruction
WREN
RDSR
READ
WRDI
RDID
RDP
PW
PP
PE
SE
DP
Write Enable
Write Disable
Read Identification
Read Status Register
Read Data Bytes
Page Write
Page Program
Page Erase
Sector Erase
Deep Power-down
Release from Deep Power-down
Description
Table 4.
One-byte Instruction Code
0000 0110
0000 0100
1001 1111
0000 0101
0000 0011
0000 1011
0000 1010
0000 0010
1101 1011
1101 1000
1011 1001
1010 1011
quence. Chip Select (S) can be driven High after
any bit of the data-out sequence is being shifted
out.
In the case of a Page Write (PW), Page Program
(PP), Page Erase (PE), Sector Erase (SE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Power-
down (RDP) instruction, Chip Select (S) must be
driven High exactly at a byte boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S) must driven High when the
number of clock pulses after Chip Select (S) being
driven Low is an exact multiple of eight.
All attempts to access the memory array during a
Write cycle, Program cycle or Erase cycle are ig-
nored, and the internal Write cycle, Program cycle
or Erase cycle continues unaffected.
DBh
D8h
ABh
9Fh
0Bh
0Ah
B9h
06h
04h
05h
03h
02h
Address
Bytes
0
0
0
0
3
3
3
3
3
3
0
0
Dummy
Bytes
0
0
0
0
0
1
0
0
0
0
0
0
1 to 256
1 to 256
Bytes
1 to 3
1 to
1 to
1 to
Data
0
0
0
0
0
0