M45PE10-07 STMICROELECTRONICS [STMicroelectronics], M45PE10-07 Datasheet
M45PE10-07
Related parts for M45PE10-07
M45PE10-07 Summary of contents
Page 1
... JEDEC standard two-byte signature (4011h) Deep Power-down mode 1 µA (typical) More than 100 000 Write cycles More than 20 years’ data retention Packages – ECOPACK® (RoHS compliant) February 2007 SO8N (MN) 150 mil width VFQPN8 (MP) (MLP8) Rev 5 M45PE10 1/45 www.st.com 1 ...
Page 2
... A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Active Power, Standby Power and Deep Power-Down modes . . . . . . . . . 13 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 2/45 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 M45PE10 ...
Page 3
... M45PE10 6.4.2 6.5 Read Data Bytes (READ 6.6 Read Data Bytes at Higher Speed (FAST_READ 6.7 Page Write (PW 6.8 Page Program (PP 6.9 Page Erase (PE 6.10 Sector Erase (SE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down (RDP Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
Page 4
... Table 14. AC characteristics (50 MHz operation Table 15. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 16. MLP8, 8-lead Very thin Dual Flat Package No lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 17. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4/45 M45PE10 ...
Page 5
... M45PE10 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO and VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 6. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 19 Figure 9 ...
Page 6
... Description 1 Description The M45PE10 Mbit (128 bit) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle ...
Page 7
... M45PE10 Table 1. Signal names Signal name Reset Function Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Reset Supply Voltage Ground Description Direction Input Input Output Input Input Input 7/45 ...
Page 8
... This input signal puts the device in the Hardware Protected mode, when Write Protect (W) is connected them from write, program and erase operations. When Write Protect (W) is connected the first 256 pages of memory behave like the other pages of memory. CC 8/45 , causing the first 256 pages of memory to become read-only by protecting M45PE10 ...
Page 9
... M45PE10 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal description 9/45 ...
Page 10
... R R Device S W HOLD Figure 3) ensures that no device is selected if the Bus requirement is met. SHCH Figure 4, is the clock polarity when the SPI Memory SPI Memory R Device Device HOLD W M45PE10 HOLD AI12836b ...
Page 11
... M45PE10 The typical value 100 k , assuming that the time constant R*C capacitance of the bus line) is short enough, as the S and C lines must reach the correct state (S = High and C = Low) while the SPI bus is in high impedance. Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µ ...
Page 12
... For optimized timings recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes (see characteristics (50 MHz 12/45 operation)). M45PE10 PW Page Write (PW) and ...
Page 13
... M45PE10 4.3 A fast way to modify data The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be: when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier Page Erase (PE) or Sector Erase (SE) instruction ...
Page 14
... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M45PE10 features the following data protection mechanisms: Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
Page 15
... M45PE10 5 Memory organization The memory is organized as: 512 pages (256 bytes each). 131,072 bytes (8 bits each) 2 sectors (512 Kbits, 65536 bytes each) Each page can be individually: programmed (bits are programmed from erased (bits are erased from written (bits are changed to either The device is Page or Sector Erasable (bits are erased from ...
Page 16
... Memory organization Figure 5. Block diagram Reset W Control Logic Address Register and Counter 16/45 High Voltage Generator I/O Shift Register 256 Byte Data Buffer 10000h 00000h 256 Bytes (Page Size) X Decoder M45PE10 Status Register 1FFFFh First 256 Pages can be made read-only 000FFh AI07405 ...
Page 17
... M45PE10 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C) ...
Page 18
... Figure 7. Write Disable (WRDI) instruction sequence 18/45 (Figure 6) sets the Write Enable Latch (WEL) bit Instruction High Impedance AI02281E (Figure 7) resets the Write Enable Latch (WEL) bit Instruction High Impedance AI03750D M45PE10 ...
Page 19
... M45PE10 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (40h), and the memory capacity of the device in the second byte (11h) ...
Page 20
... Read Status Register (RDSR) instruction sequence and data-out sequence High Impedance Q 20/45 Figure Instruction Status Register Out MSB 9. ( WEL Status Register Out MSB M45PE10 b0 (1) WIP 7 AI02031E ...
Page 21
... M45PE10 6.5 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
Page 22
... Instruction 24 BIT ADDRESS Dummy Byte DATA OUT MSB , during the falling edge of Serial Clock (C DATA OUT MSB M45PE10 MSB AI04006 ...
Page 23
... M45PE10 6.7 Page Write (PW) The Page Write (PW) instruction allows bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
Page 24
... Data Byte 2 Data Byte MSB Data Byte MSB Data Byte MSB M45PE10 AI04045 ...
Page 25
... M45PE10 6.8 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
Page 26
... Data Byte 2 Data Byte MSB Data Byte MSB Data Byte MSB M45PE10 AI04044 ...
Page 27
... M45PE10 6.9 Page Erase (PE) The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
Page 28
... Figure 15. Sector Erase (SE) instruction sequence Address bits A23 to A17 are Don’t Care. 28/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 15 Instruction 23 22 MSB Bit Address AI03751D M45PE10 ) is SE ...
Page 29
... M45PE10 6.11 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. ...
Page 30
... Figure 17. Release from Deep Power-down (RDP) instruction sequence 30/45 Figure 17 Instruction High Impedance Deep Power-down Mode M45PE10 , the device is put in the RDP t RDP Stand-by Mode AI06807 ...
Page 31
... M45PE10 7 Power-up and power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay Power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included ...
Page 32
... These parameters are characterized only, over the temperature range –40°C to +85°C. 32/45 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW threshold WI Parameter M45PE10 Read Access allowed Device fully accessible time AI04009C Min. Max. 30 ...
Page 33
... M45PE10 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). All usable Status Register bits are 0. 9 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied ...
Page 34
... Timing Reference Levels 0.8V CC 0.2V CC Parameter Test condition V OUT =25°C and a frequency of 20 MHz. A Min. Max. 2.7 3.6 –40 85 Min. Max 0. 0. Input and Output 0.7V CC 0.3V CC AI00825B Min. Max M45PE10 Unit V °C Unit Unit pF pF ...
Page 35
... M45PE10 Table 11. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO Standby current I (Standby and Reset CC1 modes) Deep Power-down I CC2 current Operating current I CC3 (FAST_READ) I Operating current (PW) CC4 I Operating current (SE) CC5 V Input low voltage IL V Input high voltage ...
Page 36
... Sector Erase cycle time (max). C Table 8 and Table 9 Min. Typ. Max. D. 200 100 10.2+ n*0.8/256 1.2 5 0.4+ n*0.8/256 M45PE10 Unit MHz MHz µs µ ...
Page 37
... M45PE10 Table 13. AC characteristics (33 MHz operation) 33 MHz only available for products marked since week 40 of 2005 Symbol Alt ( CLH ( CLL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL ...
Page 38
... Table 8 Parameter (4) (peak to peak) C (2) and Table 9 Min. Typ. Max. D. 100 0 50 100 11 0.8 int(n/8) × 0.025 10 1 M45PE10 Unit 50 MHz 33 MHz µs 30 µs 10 µs 3 µ ...
Page 39
... M45PE10 Figure 20. Serial input timing S tCHSL C tDVCH D High Impedance Q Figure 21. Write Protect setup and hold timing W tWHSL High Impedance Q tSLCH tCHSH tCHDX tCLCH MSB IN DC and AC parameters tSHSL tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 39/45 ...
Page 40
... DC and AC parameters Figure 22. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D Figure 23. Reset AC waveforms S Reset 40/45 tCH tCLQV tQLQH tQHQL tSHRH tRHSL tRLRH M45PE10 tCL tSHQZ LSB OUT AI01449e AI06808 ...
Page 41
... M45PE10 11 Package mechanical Figure 24. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 15. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data Symbol ccc ...
Page 42
... ddd C inches Typ Min 0.0335 0.0315 0.0000 0.0256 0.0079 0.0157 0.0138 0.2362 0.2264 0.1339 0.1260 0.1969 0.1870 0.1575 0.1496 0.0500 – 0.0039 0.0000 0.0236 0.0197 M45PE10 70-ME Max 0.0394 0.0020 0.0189 0.1417 0.1693 – 0.0295 12° 0.0059 0.0039 0.0020 ...
Page 43
... ST Sales Office. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Part numbering M45PE10 – ...
Page 44
... Table operation). An easy way to modify data, Page Write (PW) and Page Program values in Table 11: DC CC3 scheme. Added (Table 14 VSS ground descriptions added. modified and explanatory text added. ratings. Figure 22: Output timing. Plating technology in Table 17: Ordering Section 11: Package M45PE10 added). mechanical). ...
Page 45
... M45PE10 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...