MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 161

• Manufacturer Part Number: MC68HC908KX2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

11.4 Functional Description
11.5 I/O Signals
11.5.1 CGMXCLK
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
NOTE:
NOTE:
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
generates an asynchronous reset after 2
cycles, depending on the state of the COP rate select bit, COPRS, in the
configuration register. With a 2
4.9152-MHz CGMXCLK frequency gives a COP timeout period of
53.3 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 5–12 of
the prescaler.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls an internal reset for 64 CGMXCLK cycles and sets the
COP bit in the system integration module (SIM) reset status register
(SRSR).
In monitor mode, the COP is disabled if the IRQ1 pin is held at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
CGMXCLK is the internal clock generator (ICG) module’s oscillator
output signal. CGMXCLK is selected from either the internal clock
source or the external crystal.
Computer Operating Properly Module (COP)
18
–2
Computer Operating Properly Module (COP)
4
CGMXCLK cycle overflow option, a
13
–2
4
or 2
18
Functional Description
–2
4
Figure
CGMXCLK
Technical Data
11-1.
TST
.
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