MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 139
MC68HC908KX2
Manufacturer Part Number
MC68HC908KX2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908KX2.pdf
(311 pages)
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8.4.1 Polled LVI Operation
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
Once an LVI reset occurs, the MCU remains in reset until V
above a voltage, V
Section 6. System Integration Module (SIM)
sequence.
The output of the comparator controls the state of the LVIOUT flag in the
LVI status register (LVISR) and can be used for polling LVI operation
when the LVI reset is disabled.
In applications that can operate at V
software can monitor V
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
FROM CONFIG
DETECTOR
LVI5OR3
LOW V
V
DD
DD
Low-Voltage Inhibit (LVI)
Figure 8-1. LVI Module Block Diagram
V
V
TRIPR
DD
DD
FROM CONFIG
> LVITRIP = 0
LVIPWRD
LVITRIP = 1
DD
, which causes the MCU to exit reset. See
by polling the LVIOUT bit. In the configuration
LVIOUT
DD
STOP INSTRUCTION
levels below the V
FROM CONFIG
LVIRSTD
for the reset recovery
Low-Voltage Inhibit (LVI)
Functional Description
TRIPF
FROM CONFIG
Technical Data
LVI RESET
LVISTOP
DD
level,
rises
139
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