MC68HC908KX2 MOTOROLA [Motorola, Inc], MC68HC908KX2 Datasheet - Page 123

• Manufacturer Part Number: MC68HC908KX2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.5.6.1 Settling to Within 15 Percent
7.5.6.2 Settling to Within 5 Percent
MC68HC908KX8 • MC68HC908KX2 • MC68HC08KX8 — Rev. 1.0
MOTOROLA
When the error is greater than 15 percent, the filter takes eight
corrections to double or halve the clock period. Due to how the DCO
increases or decreases the clock period, the total period of these eight
corrections is approximately 11 times the period of the fastest correction.
(If the corrections were perfectly linear, the total period would be 11.5
times the minimum period; however, the ring must be slightly nonlinear.)
Therefore, the total time it takes to double or halve the clock period is
44*N*
If the clock period needs more than doubled or halved, the same
relationship applies, only for each time the clock period needs doubled,
the total number of cycles doubles. That is, when transitioning from fast
to slow, going from the initial speed to half speed takes 44*N*
from half speed to quarter speed takes 88*N*
quarter speed to eighth speed takes 176*N*
series can be expressed as (2
number of times the speed needs doubled or halved. Since 2
to be equal to
44*N*(
Note that increasing speed takes much longer than decreasing speed
since N is higher. This can be expressed in terms of the initial clock
period (
Once the clock period is within 15 percent of the desired clock period,
the filter starts making smaller adjustments. When between 15 percent
and 5 percent error, each correction will adjust the clock period between
1.61 percent and 2.94 percent. In this mode, a maximum of eight
corrections will be required to get to less than 5 percent error. Since the
clock period is relatively close to desired, each correction takes
approximately the same period of time, or 4*
internal clock stable bit (ICGS) will be set and the clock frequency is
ICLKFAST
Internal Clock Generator Module (ICG)
ICLKSLOW
1
) minus the final clock period (
ICLKSLOW
.
–
ICLKFAST
15
/
ICLKFAST
=
).
abs 44N
x
–1)*44*N*
, the equation reduces to
Internal Clock Generator Module (ICG)
2
1
) as such:
ICLKFAST
–
ICLKFAST
IBASE
2
ICLKFAST
. At this point, the
, where x is the
; and so on. This
; going from
Technical Data
Usage Notes
x
ICLKFAST
happens
123
;