LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 89

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
Chapter 16 Runtime Registers
16.1
Notes :
16.2
SMSC DS – LPC47N237
Hard Reset: nPCI_RESET pin asserted.
Reserved bits return 0 on read.
NAME/DEFAULT
PME_STS
Default = 0x00
on VTR POR
PME_EN
Default = 0x00
on VTR POR
REGISTER
OFFSET
(hex)
00
01
02
03
Runtime Registers Block Summary
The runtime registers are located at the address programmed in the Runtime Register Block Base Address
configuration registers located in CR2F and CR30. The part performs 16-bit address qualification on the
Runtime Register Base Address (bits[11:0] are decoded and bits[15:12] must be zero). The runtime
register block may be located within the range 0x0100-0x0FFC on 4-byte boundaries. Decodes are
disabled if the Runtime Register Base Address is located below 0x100. These registers are powered by
VTR.
Runtime Registers Block Description
TYPE
R/W
R/W
R/W
R
OFFSET (TYPE)
REGISTER
(R/W)
(R/W)
Table 16.2 – Runtime Registers Block Description
0x00
0x01
RESET
HARD
Table 16.1 - Runtime Register Block Summary
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DATASHEET
VCC POR
Bit[0] RI_PME_Status
= 0 (default)
= 1 Set when nRI1 transitions from high-to-low. If the
RI_PME_EN bit is set, nIO_PME pin will be active.
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or HARD
RESET.
Writing a “1” to PME_Status will clear it and will stop asserting
nIO_PME, if enabled. Writing a “0” to PME_Status has no effect.
Bit[0] RI_PME_EN
= 0 nRI wake event disabled
= 1 nRI wake event enabled
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or HARD
RESET
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Page 89
VTR POR
0x00
0x00
0x00
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PME_STS
PME_EN
LGP_DATA
Reserved – read only, read returns 0.
DESCRIPTION
REGISTER
Revision 0.3 (10-26-04)