LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 75

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
Chapter 13 LPC General Purpose I/O
13.1
Note 13.1
13.2
SMSC DS – LPC47N237
The LPC47N237 provides a set of flexible Input/Output control functions to the system designer through
the 4 independently programmable LPC controlled General Purpose I/O pins (LGP44-LGP47). The LPC
GPIOs are VCC powered and are not available under VTR power only.
Description
Each LPC GPIO port has a 1-bit data register. GPIOs are controlled by GPIO control registers located in
the Configuration section. The data register for each GPIO port is represented as a bit in one of the 8-bit
GPIO DATA Register, LGP_DATA. The bits in the registers reflect the value of the associated GPIO pin
as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the
bit goes to the GPIO pin. Latched on read and write. The GPIO data registers are located in the Runtime
Register block; see the Runtime Registers section.
GPIO Control
Each GPIO port has an 8-bit control register that controls the behavior of the pin. This register is defined
in the Configuration section of this specification.
Each GPIO port may be configured as either an input or an output. If the pin is configured as an output, it
will be push-pull. Inputs and outputs can be configured as non-inverting or inverting. LPC GPIO Direction
Register determine the port direction and LPC GPIO Polarity Register determine the signal polarity.
The basic GPIO configuration options are summarized in Table 13.2.
The GPIO Data Registers are located at the offset shown from the RUNTIME REGISTERS BLOCK
address.
Reserved
Reserved
Reserved
Reserved
LGP44
LGP45
LGP46
LGP47
FUNCTION
DEFAULT
Table 13.1 – General Purpose I/O Port Assignments
LGP_DATA
REGISTER
(NOTE 13.1
DATA
DATASHEET
)
Page 75
DATA REGISTER
BIT NO.
0
1
2
3
4
5
6
7
OFFSET (HEX)
REGISTER
02
Revision 0.3 (10-26-04)