LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 135

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

3.3v I/O Controller for Port Replicators and Docking Stations
Chapter 21 XNOR-Chain Test Mode
21.1
21.1.1 XNOR-Chain test mode can be entered as follows:
21.1.2 XNOR-Chain test mode can be exited as follows:
SMSC DS – LPC47N237
I/O#1
The LPC47N237 provides board test capability through the implementation of XNOR chain. See following
sub-sections.
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during
assembly and test operations. See Figure 21.1 below. When the chip is in the XNOR chain test mode,
setting the state of any of the input pins to the opposite of its current state will cause the output of the chain
to toggle.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is
activated, the LPC47N237 pin functions are disconnected from the device pins, which all become input
pins except for one output pin at the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level test
hardware to control the device pins and observe the results at the XNOR-Chain output pin.
Entering and Exiting Test Mode
On the rising (deasserting) edge of nPCI_RESET, drive nLFRAME low and drive LAD[0] low.
On the rising (deasserting) edge of nPCI_RESET, drive either nLFRAME or LAD[0] high.
The nPCI_RESET pin is not included in the XNOR-Chain. The XNOR-Chain output pin# is 17, nIO_PME.
See the following subsections for more details.
I/O#2
Figure 21.1 – XNOR-CHAIN TEST STRUCTURE
DATASHEET
I/O#3
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I/O#n
Revision 0.3 (10-26-04)
XNor
Out