LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 24

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

Chapter 7
7.1
7.2
Note:
7.3
Revision 0.3 (10-26-04)
Refer to the configuration registers description for setting the base addresses.
The following sections describe the functional blocks located in the LPC47N237 (see Figure 5.1). All the
functional blocks are dedicated to the Super I/O portion of the chip, except the SMBus GPIO Block. The
SMBus GPIO Block is maintained separately from the Super I/O components and is defined in the “SMBus
GPIO Block” section. The various Super I/O components are described in the following sections and their
registers are implemented as typical Plug-and-Play components (see “Configuration” section). The SMBus
GPIO Block registers are accessible via the SMBus slave address and are defined in the “SMBus GPIO
Register Map” section.
functionality is required). The SMBus GPIO Block is powered by VTR.
It should be noted that there are two main interfaces used to access the components of this chip. The LPC
interface is used to access the Super I/O registers and the SMBus is used to access the SMBus GPIO
registers.
Super I/O Registers
The address map, shown below in Table 7.1, shows the addresses of the different blocks of the Super I/O
immediately after power up. The base addresses of the Serial Port, and Parallel Port, Runtime Register
Block and Configuration Register block can be moved via the configuration registers. Some addresses are
used to access more than one register.
Host Processor Communication
The host processor communicates with the LPC47N237 through a series of read/write registers via the
LPC interface.
accomplished through I/O cycles or DMA transfers. All registers are 8 bits wide.
LPC Interface
The following sub-sections specify the implementation of the LPC bus.
Functional Description
The port addresses for these registers are shown in Table 7.1. Register access is
Base+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Base + (0-3)
Base + (0-1)
The Super I/O components is powered by VCC and VTR (where wakeup
Table 7.1 - Super I/O Block Addresses
ADDRESS
DATASHEET
Page 24
Serial Port
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
Runtime Registers
Configuration
BLOCK NAME
3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS – LPC47N237