LPC47N237-MD SMSC [SMSC Corporation], LPC47N237-MD Datasheet - Page 22

• Manufacturer Part Number: LPC47N237-MD
• Description: 3.3V I/O CONTROLLER FOR PORT REPLICATORS AND DOCKING STATIONS
• Manufacturer: SMSC [SMSC Corporation]

6.3.1
6.4
6.5
6.6
Revision 0.3 (10-26-04)
Trickle Power Functionality
The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.
The following list summarizes the blocks, registers and pins that are powered by VTR.
24 MHz Crystal
The LPC47N237 utilizes 24 MHz crystal pins XTAL1 and XTAL2. The XTAL1 pin can also be used to as a
single-ended clock source pin provided that XTAL2 is left unconnected. The 24 MHz clock is used to
generate specific clock needed for various logic in the Super I/O Block. This clock also is also used for the
SMBus GPIO Block. The XTAL1 and XTAL2 pins are powered by VTR and this clock source is available
both when VCC is active and when the part is under VTR power only (VCC=0).
24 MHz Output
The 24MHz_OUT is a 24 MHz clock output pin and is powered by VCC. This clock in not available when
VCC = 0.
Internal PWRGOOD
An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the
host interface as V
(nominal), and the LPC47N237 host interface is active. When the internal PWRGOOD signal is “0”
I/O buffers that are not wake-up compatible are powered by VCC. In the absence of VCC they are
backdrive protected (they do not impose load on any VTR powered circuitry). These pins do not have
input buffers into the wakeup logic that are powered by VTR, and are not used for wakeup.
I/O buffers that are wake-up event compatible are powered by VTR. These pins have input buffers
into the wakeup logic that are powered by VTR.
I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are
powered by VTR. This means they will, at a minimum, source their specified current from VTR even
when VCC is present.
Blocks and Pins in SIO Block
PME interface block
Runtime register block (includes PME and GP data registers)
Pins for PME Wakeup:
− nIO_PME
− nRI
XTAL1 and XTAL2 pins
SMBus GPIO Block
− SMBus Controller
− GPIO Block
− Pins
GP10-GP30, GP50-GP57. These GPIOs can be used to detect an edge on the pin and can be driven
under VTR power.
SCLK, SDAT, SMB_A0, nSMBINT, SCLK_1, SDAT_1, SCLK_2, SDAT_2
CC
cycles on and off. When the internal PWRGOOD signal is “1” (active), V
DATASHEET
Page 22
3.3v I/O Controller for Port Replicators and Docking Stations
SMSC DS – LPC47N237
CC
> 2.3V