FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 70

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

LOCK
In order to protect systems with long DMA
latencies against older application software that
can disable the FIFO the LOCK Command has
been added. This command should only be used
by the FDC routines, and application software
should refrain from using it. If an application calls
for the FIFO to be disabled then the CONFIGURE
command should be used.
The LOCK command defines whether the EFIFO,
FIFOTHR, and PRETRK parameters of the
CONFIGURE command can be RESET by the
DOR and DSR registers. When the LOCK bit is
set to logic "1" all subsequent "software RESETS
by the DOR and DSR registers will not change the
previously set parameters to their default values.
All "hardware" RESET from the RESET pin will set
the LOCK bit to logic "0" and return the EFIFO,
FIFOTHR, and PRETRK to their default values. A
status byte is returned immediately after issuing a
LOCK command. This byte reflects the value of
the LOCK bit set by the command byte.
ENHANCED DUMPREG
The DUMPREG command is designed to support
system run-time diagnostics and application
software
accommodate the LOCK command and the
enhanced PERPENDICULAR MODE command
The chip incorporates two full function UARTs.
They are compatible with the NS16450, the 16450
ACE registers and the NS16C550A. The UARTS
perform serial-to-parallel conversion on received
characters and parallel-to-serial conversion on
transmit
independently programmable from 460.8K baud
down to 50 baud.
programmable for 1 start; 1, 1.5 or 2 stop bits;
even, odd, sticky or no parity; and prioritized
interrupts.
programmable baud rate generator that is capable
of dividing the input clock or crystal by a number
from 1 to 65535. The UARTs are also capable of
supporting the MIDI data rate. Refer to the
Configuration
characters.
development
The
Registers
UARTs
The character options are
The
for
and
each
data
information
debug.
contain
SERIAL PORT (UART)
rates
are
To
on
a
70
the eighth byte of the DUMPREG command has
been modified to contain the additional data from
these two commands.
COMPATIBILITY
This
compatibility in mind.
compatible solution with the older generation
765A/B
implements on-board registers for compatibility
with the PS/2, as well as PC/AT and PC/XT,
floppy disk controller subsystems. After a
hardware reset of the FDC, all registers,
functions and enhancements default to a PC/AT,
PS/2 or PS/2 Model 30 compatible operating
mode, depending on how the IDENT and MFM
bits are configured by the system BIOS.
Force Write Protect
The Force Write Protect function forces the FDD
nWRTPRT input active if the FORCE WRTPRT
bit is active. The Force Write Protect function
applies to the nWRTPRT pin in the FDD
Interface as well as the nWRTPRT pin in the
Parallel Port FDC.
Register L8CR_C5 for more information.
disabling, power down and changing the base
address of the UARTs.
UART is enabled by programming OUT2 of that
UART to a logic "1".
disables that UART's interrupt. The second UART
also supports IrDA 1.0, HP-SIR, ASK-IR and
Consumer IR infrared modes of operation.
Note: The UARTs may be configured to share an
interrupt. Refer to the Configuration section for
more information.
REGISTER DESCRIPTION
Addressing of the accessible registers of the Serial
Port is shown below. The configuration registers
chip
disk
was
controllers.
designed
OUT2 being a logic "0"
It is a fully backwards-
Refer to Configuration
The interrupt from a
The
with
FDC
software
also