FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 43

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

POLL
PRETRK
R
RCN
SC
SK
SRT
ST0
ST1
ST2
ST3
WGATE
Polling Disable
Precompensation
Start Track
Number
Sector Address
Relative Cylinder
Number
Number of Sectors
Per Track
Skip Flag
Step Rate Interval
Status 0
Status 1
Status 2
Status 3
Write Gate
TABLE 21 - DESCRIPTION OF COMMAND SYMBOLS
The sector number to be read or written. In multi-sector transfers,
The time interval between step pulses issued by the FDC.
Alters timing of WE to allow for pre-erase loads in perpendicular
When set, the internal polling routine is disabled. When clear, polling
is enabled.
Programmable from track 00 to FFH.
this parameter specifies the sector number of the first sector to be
read or written.
Relative cylinder offset from present cylinder as used by the Relative
Seek command.
The number of sectors per track to be initialized by the Format
command. The number of sectors per track to be verified during a
Verify command when EC is set.
When set to 1, sectors containing a deleted data address mark will
automatically be skipped during the execution of Read Data. If Read
Deleted is executed, only sectors with a deleted address mark will be
accessed. When set to "0", the sector is read or written the same as
the read and write commands.
Programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at
the 1 Mbit data rate. Refer to the SPECIFY command for actual
delays.
Registers within the FDC which store status information after a
command has been executed. This status information is available to
the host during the result phase after command execution.
drives.
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