FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 31

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

PS/2 Mode
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps
data rates are selected, and high when 250 Kbps
and 300 Kbps are selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are
software reset, and are set to 250 Kbps after a
hardware reset.
RESET
COND.
See Table 11 for the settings
CHG
DSK
N/A
7
unaffected by
N/A
6
1
N/A
5
1
a
31
N/A
4
1
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk cable
or the value programmed in the Force Disk
Change Register (see Configuration Register
LD8:CRC1[1:0]).
N/A
3
1
DRATE
SEL1
N/A
2
DRATE
SEL0
N/A
1
nDENS
nHIGH
0
1