FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 166

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

CONFIGURATION
The Configuration of the FDC37B78x is very
flexible and is based on the configuration
architecture implemented in typical Plug-and-Play
components. The FDC37B78x is designed for
motherboard applications in which the resources
required by their components are known. With its
flexible
FDC37B78x allows the BIOS to assign resources
at POST.
SYSTEM ELEMENTS
Primary Configuration Address Decoder
After a hard reset (RESET_DRV pin asserted) or
Vcc Power On Reset the FDC37B78x is in the
Run Mode with all logical devices disabled. The
logical devices may be configured through two
standard Configuration I/O
DATA)
Configuration Mode.
Note 1: If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use 10K pull-down.
Note 2: The configuration port base address can be relocated through CR26 and CR27.
CONFIG PORT (Note 2)
INDEX PORT (Note 2)
DATA PORT
DEV_INT
Interface
to nPME
out to pin
or Serial
Logic
nSMI
IRQ2
resource
PORT NAME
by
placing
allocation
EN_SMI_PME
SMI_EN2 Register
EN_SMI
of SMI_EN2
Register
The BIOS uses these
Bit 7
Bit 6 of
the FDC37B78x into
Group
SMI
Ports
0x03F0
INDEX PORT + 1
0x03F0
architecture,
(Pull-down resistor)
FIGURE 6 - SMI/PME LOGIC
(INDEX and
Refer to Note 1
SYSOPT= 0
the
168
0xF0 of Logical Device A.
Bit 0 of the Sleep Enable
Configuration Register
configuration ports to initialize the logical devices
at POST. The INDEX and DATA ports are only
valid when the FDC37B78x is in Configuration
Mode.
The SYSOPT pin is latched on the falling edge of
the RESET_DRV or on Vcc Power On Reset to
determine
address. The SYSOPT pin is used to select the
CONFIG PORT's I/O address at power-up. Once
powered up the configuration port base address
can be changed through configuration registers
CR26 and CR27.
hardware configuration pin which is shared
with the nRTS1 signal on pin 115. During reset
this pin is a weak active low signal which sinks
30µA. Note: All I/O addresses are qualified with
AEN.
The INDEX and DATA ports are effective only
when the chip is in the Configuration State.
SMI_EN1 Register
SMI_EN2 Register
SLP_CTRL
Registers
SMI_EN
EN_PINT
EN_U2INT
EN_U1INT
EN_FINT
EN_GPINT2
EN_GPINT1
EN_WDT
EN_RING
EN_MINT
EN_KINT
EN_IRINT
EN_BINT
EN_P12
EN_CIR
0x0370
0x0370
(10K Pull-up resistor)
the
SYSOPT= 1
SMI_STS1 Register
SMI_STS2 Register
Registers
SMI_STS
configuration
SLP_EN_SMI
PINT
U2INT
U1INT
FINT
GPINT2
GPINT1
WDT
MINT
KINT
IRINT
BINT
P12
Key to Symbols
The SYSOPT
Enable bit
Interrupt Status bit: Cleared at
source
Interrupt Status bit: Cleared by
a read of register
Sticky Status bit: Cleared by a
write of ‘1’ to this bit
CIR Bit, PME_STS1 Register
RING Bit, PME_STS1 Register
register's
EVENT
Write
Read/Write
Read/Write
nRING
PINT
U2INT
U1INT
FINT
GPINT2
GPINT1
WDT
MINT
KINT
IRINT
BINT
P12
CIR
SLP_EN
TYPE
pin
base
is a