FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 180

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

Interrupt Select Configuration Register
Note:
Note:
Note:
Interrupt
Request Level
Select 0
Default = 0x00
on Vcc POR or
Reset_Drv
for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
for the Serial Port logical device by setting any combination of bits D0-D3 in the IER
and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
for the RTC by (refer to the RTC section of this spec.)
for the KYBD by (refer to the KYBD controller section of this spec.)
NAME
It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ
number.
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND:
IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.
TABLE 74 - INTERRUPT SELECT CONFIGURATION REGISTER DESCRIPTION
0x70 (R/W)
REG INDEX
Bits[3:0] selects which interrupt level is used for
Interrupt 0.
0x00=no interrupt selected.
0x01=IRQ1
0x02=IRQ2
0x0E=IRQ14
0x0F=IRQ15
Note: All interrupts are edge high (except ECP/EPP)
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DEFINITION
STATE
C