FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 173
FDC37B787QF
Manufacturer Part Number
FDC37B787QF
Description
Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.FDC37B787QF.pdf
(249 pages)
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Chip Level (Global) Control/Configuration Registers [0x00-0x2F]
The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of
the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return
zero when read. The INDEX PORT is used to select a configuration register in the chip. The DATA PORT
is then used to access the selected register. These registers are accessable only in the Configuration
Mode.
Config Control
Default = 0x00
on Vcc POR or
Reset_Drv
Index Address
Default = 0x03
on Vcc POR or
Reset_Drv
Logical Device #
Default = 0x00
on Vcc POR or
Reset_Drv
Card Level
Reserved
REGISTER
0x04 - 0x06
0x08 - 0x1F
ADDRESS
0x03 R/W
0x07 R/W
0x02 W
0x00 -
0x01
TABLE 71 - CHIP LEVEL REGISTERS
Reserved - Writes are ignored, reads return 0.
The hardware automatically clears this bit after the
write, there is no need for software to clear the bits.
Bit 0 = 1: Soft Reset.
Registers" table for the soft reset value for each
register.
Bit[7]
= 1 Enable GP1, WDT_CTRL, GP5, GP6, Soft Power
Enable and Status Register access when not in
configuration mode
= 0 Disable GP1, WDT_CTRL, GP5, GP6, Soft Power
Enable and Status Register access when not in
configuration mode (Default)
Bits [6:2]
Reserved - Writes are ignored, reads return 0.
Bits[1:0]
Sets GP1 etc. selection register used when in Run
mode (not in Configuration Mode).
= 11 0xEA (Default)
= 10 0xE4
= 01 0xE2
= 00 0xE0
Reserved - Writes are ignored, reads return 0.
A write to this register selects the current logical
device.
configuration registers for each logical device. Note:
the Activate command operates only on the selected
logical device.
Reserved - Writes are ignored, reads return 0.
Chip (Global) Control Registers
Chip Level, SMSC Defined
This allows access to the control and
176
DESCRIPTION
Refer to the "Configuration
STATE
C
C
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