LAN9311i SMSC [SMSC Corporation], LAN9311i Datasheet - Page 5
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LAN9311i
Manufacturer Part Number
LAN9311i
Description
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN9311I.pdf
(459 pages)
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Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10 PHY Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.11 LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.12 Required Ethernet Magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.3
7.3.1
7.3.2
Chapter 8 Host Bus Interface (HBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.1
8.2
8.3
8.3.1
8.3.2
8.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
SMSC LAN9311/LAN9311i
7.2.1.6
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.2.5
7.2.2.6
7.2.2.7
7.2.3.1
7.2.3.2
7.2.4.1
7.2.4.2
7.2.4.3
7.2.4.4
7.2.5.1
7.2.5.2
7.2.5.3
7.2.5.4
7.2.5.5
7.2.8.1
7.2.9.1
7.2.9.2
7.2.10.1
7.2.10.2
7.2.10.3
7.3.1.1
7.3.1.2
7.3.1.3
7.3.2.1
7.3.2.2
7.3.2.3
8.5.1.1
8.5.1.2
8.5.1.3
Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Host Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Host Data Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Host Endianess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
100BASE-TX Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10BASE-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10BASE-T Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PHY Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
MII MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PHY Management Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Virtual PHY Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Virtual PHY Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
16-Bit Bus Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
16-Bit Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Special Situations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Special Restrictions on Back-to Back Write-Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
RX Data FIFO Direct PIO Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TX Data FIFO Direct PIO Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
100M Phase Lock Loop (PLL) ........................................................................................................................................................................ 86
A/D Converter ................................................................................................................................................................................................. 87
DSP: Equalizer, BLW Correction and Clock/Data Recovery .......................................................................................................................... 87
NRZI and MLT-3 Decoding ............................................................................................................................................................................. 88
Descrambler and SIPO ................................................................................................................................................................................... 88
5B/4B Decoding .............................................................................................................................................................................................. 88
Receiver Errors ............................................................................................................................................................................................... 88
MII MAC Interface ........................................................................................................................................................................................... 88
MII MAC Interface ........................................................................................................................................................................................... 89
10M TX Driver and PLL .................................................................................................................................................................................. 89
Filter and Squelch ........................................................................................................................................................................................... 89
10M RX and PLL............................................................................................................................................................................................. 89
MII MAC Interface ........................................................................................................................................................................................... 90
Jabber Detection............................................................................................................................................................................................. 90
PHY Pause Flow Control ................................................................................................................................................................................ 92
Parallel Detection............................................................................................................................................................................................ 92
Restarting Auto-Negotiation............................................................................................................................................................................ 92
Disabling Auto-Negotiation ............................................................................................................................................................................. 92
Half Vs. Full-Duplex ........................................................................................................................................................................................ 93
PHY Interrupts ................................................................................................................................................................................................ 94
PHY General Power-Down ............................................................................................................................................................................. 95
PHY Energy Detect Power-Down ................................................................................................................................................................... 95
PHY Software Reset via RESET_CTL............................................................................................................................................................ 95
PHY Software Reset via PHY_BASIC_CTRL_x ............................................................................................................................................. 96
PHY Power-Down Reset................................................................................................................................................................................. 96
Parallel Detection............................................................................................................................................................................................ 97
Disabling Auto-Negotiation ............................................................................................................................................................................. 97
Virtual PHY Pause Flow Control ..................................................................................................................................................................... 98
Virtual PHY Software Reset via RESET_CTL ................................................................................................................................................ 98
Virtual PHY Software Reset via VPHY_BASIC_CTRL ................................................................................................................................... 98
Virtual PHY Software Reset via PMT_CTRL .................................................................................................................................................. 98
Reset Ending During a Read Cycle .............................................................................................................................................................. 102
Reset Ending Between Halves of a 16-Bit Read Pair ................................................................................................................................... 102
Writes Following a Reset .............................................................................................................................................................................. 102
DATASHEET
5
Revision 1.6 (08-18-09)
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