LAN9311i SMSC [SMSC Corporation], LAN9311i Datasheet - Page 198
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LAN9311i
Manufacturer Part Number
LAN9311i
Description
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN9311I.pdf
(459 pages)
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Revision 1.6 (08-18-09)
14.2.4
14.2.4.1
BITS
31
EEPROM Controller Busy (EPC_BUSY)
When a 1 is written into this bit, the operation specified in the
EPC_COMMAND field of this register is performed at the specified
EEPROM address. This bit will remain set until the selected operation is
complete. In the case of a read, this indicates that the Host can read valid
data from the
E2P_DATA registers should not be modified until this bit is cleared. In the
case where a write is attempted and an EEPROM is not present, the
EPC_BUSY bit remains set until the
(EPC_TIMEOUT)
Note:
EEPROM
This section details the EEPROM related System CSR’s. These registers should only be used if an
EEPROM has been connected to the LAN9311/LAN9311i. Refer to chapter
"I2C/Microwire Master EEPROM Controller," on page 138
modes (I
EEPROM Command Register (E2P_CMD)
This read/write register is used to control the read and write operations of the serial EEPROM.
EPC_BUSY is set immediately following power-up, or pin reset, or
DIGITAL_RST reset. This bit is also set following the settings of the
SRST bit in the
the EEPROM Loader has finished loading, the EPC_BUSY bit is
cleared. Refer to chapter
page 150
Offset:
2
C and Microwire) of the EEPROM Controller (EPC).
EEPROM Data Register
bit is set. At this time the EPC_BUSY bit is cleared.
for more information.
Hardware Configuration Register
1B4h
DESCRIPTION
Section 10.2.4, "EEPROM Loader," on
EEPROM Controller Timeout
DATASHEET
(E2P_DATA). The E2P_CMD and
198
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Size:
(HW_CFG). After
for additional information on the various
32 bits
TYPE
R/W
SMSC LAN9311/LAN9311i
SC
Section 10.2,
DEFAULT
Datasheet
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