PIC18F25J11-I/PT MICROCHIP [Microchip Technology], PIC18F25J11-I/PT Datasheet - Page 219

• Manufacturer Part Number: PIC18F25J11-I/PT
• Description: 28/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

15.0
The Timer4 timer module has the following features:
• 8-Bit Timer register (TMR4)
• 8-Bit Period register (PR4)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 15-1.
Timer4 can be shut off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 is also
controlled by this register. Figure 15-1 is a simplified
block diagram of the Timer4 module.
REGISTER 15-1:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-3
bit 2
bit 1-0
U-0
—
TIMER4 MODULE
Unimplemented: Read as ‘0’
T4OUTPS<3:0>: Timer4 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR4ON: Timer4 On bit
1 = Timer4 is on
0 = Timer4 is off
T4CKPS<1:0>: Timer4 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
T4OUTPS3
R/W-0
T4CON: TIMER4 CONTROL REGISTER (ACCESS F76h)
W = Writable bit
‘1’ = Bit is set
T4OUTPS2
R/W-0
T4OUTPS1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
T4OUTPS0
PIC18F46J11 FAMILY
R/W-0
15.1
Timer4 can be used as the PWM time base for the
PWM mode of the ECCP modules. The TMR4 register
is readable and writable and is cleared on any device
Reset. The input clock (F
of 1:1, 1:4 or 1:16, selected by control bits,
T4CKPS<1:0> (T4CON<1:0>). The match output of
TMR4 goes through a 4-bit postscaler (which gives a
1:1 to 1:16 scaling inclusive) to generate a TMR4
interrupt, latched in flag bit, TMR4IF (PIR3<3>).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR4 register
• a write to the T4CON register
• any device Reset (Power-on Reset (POR), MCLR
TMR4 is not cleared when T4CON is written.
Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR))
Timer4 Operation
TMR4ON
R/W-0
OSC
x = Bit is unknown
T4CKPS1
R/W-0
/4) has a prescale option
DS39932C-page 219
T4CKPS0
R/W-0
bit 0