PIC18F25J11-I/PT MICROCHIP [Microchip Technology], PIC18F25J11-I/PT Datasheet - Page 130

• Manufacturer Part Number: PIC18F25J11-I/PT
• Description: 28/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F46J11 FAMILY
TABLE 9-3:
DS39932C-page 130
RA0/AN0/C1INA/
ULPWU/RP0
RA1/AN1/C2INA/
PMA7/RP1
RA2/AN2/
V
C2INB
RA3/AN3/V
C1INB
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
Note 1:
REF
-/CV
Pin
REF
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This bit is only available on 44-pin devices.
REF
/
+/
PORTA I/O SUMMARY
Function
ULPWU
PMA7
C1INA
C2INA
CV
C2INB
C1INB
V
V
RA0
AN0
RP0
RA1
AN1
RP1
RA2
AN2
RA3
AN3
REF
REF
REF
(1)
+
-
Setting
TRIS
1
0
1
1
1
1
0
1
0
1
1
1
0
1
0
0
1
1
1
x
I
0
0
1
1
1
1
1/O
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA A/D input channel 0 and Comparator C1- input. Default input
ANA Comparator 1 input A.
ANA Ultra low-power wake-up input.
ANA A/D input channel 1 and Comparator C2- input. Default input
ANA Comparator 1 input A.
ANA A/D input channel 2 and Comparator C2+ input. Default input
ANA A/D and comparator voltage reference low input.
ANA Comparator voltage reference output. Enabling this feature
ANA Comparator 2 input B.
ANA CTMU pulse generator charger for the C2INB comparator
ANA A/D input channel 3 and Comparator C1+ input. Default input
ANA A/D and comparator voltage reference high input.
ANA Comparator 1 input B
DIG
TTL
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
DIG
TTL
ST/
I/O
ST
ST
PORTA<0> data input; disabled when analog input enabled.
LATA<0> data output; not affected by analog input.
configuration on POR; does not affect digital output.
Remappable peripheral pin 0 input.
Remappable peripheral pin 0 output.
PORTA<1> data input; disabled when analog input enabled.
LATA<1> data output; not affected by analog input.
configuration on POR; does not affect digital output.
Parallel Master Port.
Parallel Master Port address.
Remappable peripheral pin 1 input.
Remappable peripheral pin 1 output
LATA<2> data output; not affected by analog input. Disabled
when CV
PORTA<2> data input. Disabled when analog functions
enabled; disabled when CV
configuration on POR; not affected by analog output.
disables digital I/O.
input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
configuration on POR.
REF
output enabled.
Description
REF
© 2009 Microchip Technology Inc.
output enabled.