PIC18F25J11-I/PT MICROCHIP [Microchip Technology], PIC18F25J11-I/PT Datasheet - Page 105
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PIC18F25J11-I/PT
Manufacturer Part Number
PIC18F25J11-I/PT
Description
28/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F25J11-IPT.pdf
(528 pages)
- Current page: 105 of 528
- Download datasheet (9Mb)
6.5.2
The PIC18F46J11 family of devices has a feature that
allows programming a single word (two bytes). This
feature is enabled when the WPROG bit is set. If the
memory location is already erased, the following
sequence is required to enable this feature:
1.
2.
EXAMPLE 6-4:
© 2009 Microchip Technology Inc.
PROGRAM_MEMORY
Load the Table Pointer register with the address
of the data to be written. (It must be an even
address.)
Write the 2 bytes into the holding registers by
performing table writes. (Do not post-increment
on the second table write.)
Required
Sequence
FLASH PROGRAM MEMORY WRITE
SEQUENCE (WORD PRORAMMING).
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
TBLWT*+
MOVLW
MOVWF
TBLWT*
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
BCF
SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
DATA0
TABLAT
DATA1
TABLAT
EECON1, WPROG
EECON1, WREN
INTCON, GIE
55h
EECON2
0AAh
EECON2
EECON1, WR
INTCON, GIE
EECON1, WPROG
EECON1, WREN
; Load TBLPTR with the base address
; The table pointer must be loaded with an even
; LSB of word to be written
; MSB of word to be written
; The last table write must not increment the table
; enable single word write
; enable write to memory
; disable interrupts
; write 55h
; write AAh
; start program (CPU stall)
; re-enable interrupts
; disable single word write
; disable write to memory
address
pointer! The table pointer needs to point to the
MSB before starting the write operation.
PIC18F46J11 FAMILY
3.
4.
5.
6.
7.
8.
9.
Set the WREN bit (EECON1<2>) to enable
writes and the WPROG bit (EECON1<5>) to
select Word Write mode.
Disable interrupts.
Write 55h to EECON2.
Write 0AAh to EECON2.
Set the WR bit; this will begin the write cycle.
The CPU will stall for the duration of the write for
T
Re-enable interrupts.
IW
(see parameter D133A).
DS39932C-page 105
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