ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 74

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

ADAU1373
Reg Name
38
39
3C ADC_SETTING
40
41
42
43
44
45
46
47
48
49
4A SRCA_RATIOA
4B
4C SRCB_RATIOA
4D SRCB_RATIOB
4E
4F
50
51
52
53
56
57
58
59
5A DIN_MIX_
5B
5C DOUT_MIX_
5D DOUT_MIX_
5E
5F
60
61
62
63
64
65
66
67
68
69
MIC_JACK_
STATUS
CHIP_FAULT_
STATUS
CLK1_
SOURCE_DIV
CLK1_
OUTPUT_DIV
CLK2_
SOURCE_DIV
CLK2_
OUTPUT_DIV
DAIA
DAIB
DAIC
BCLKDIVA
BCLKDIVB
BCLKDIVC
SRCA_RATIOB
SRCC_RATIOA
SRCC_RATIOB
DEEMP_CTRL
SRC_DAI_A_
CTRL
SRC_DAI_B_
CTRL
SRC_DAI_C_
CTRL
DIN_MIX_
CTRL0
DIN_MIX_
CTRL1
DIN_MIX_
CTRL2
DIN_MIX_
CTRL3
CTRL4
DOUT_MIX_
CTRL0
CTRL1
CTRL2
DOUT_MIX_
CTRL3
DOUT_MIX_
CTRL4
VOLMOD1
VOLMOD2
DAIA_PBL_
VOL
DAIA_PBR_
VOL
DAIB_PBL_
VOL
DAIB_PBR_
VOL
DAIC_PBL_
VOL
DAIC_PBR_
VOL
DAIA_RECL_
VOL
DAIA_RECR_
VOL
Bits
[7:0]
[7:0]
[7:0]
[7:0] COREN
[7:0]
[7:0] CLK2EN
[7:0]
[7:0] BCLKINVA
[7:0] BCLKINVB
[7:0] BCLKINVC
[7:0]
[7:0]
[7:0]
[7:0] SRCAMODE
[7:0]
[7:0] SRCBMODE
[7:0]
[7:0] SRCCMODE
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit 7
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit 6
CLK1S_SEL
CLK2S_SEL
MSA
MSB
MSC
DIN_CHAN0_
DMIC_SWAP
DIN_CHAN1_
DMIC_SWAP
DIN_CHAN2_
DMIC_SWAP
DIN_CHAN3_
DMIC_SWAP
DIN_CHAN4_
DMIC_SWAP
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit 5
CLK1OEN
CLK2OEN
SWAPA
SWAPB
SWAPC
DAIA_
SOURCE
DAIB_
SOURCE
DAIC_
SOURCE
SRCA_
RECWRONG
SRCB_
RECWRONG
SRCC_
RECWRONG
DIN_CHAN0_
DMIC
DIN_CHAN1_
DMIC
DIN_CHAN2_
DMIC
DIN_CHAN3_
DMIC
DIN_CHAN4_
DMIC
DAICRECVOLM
RESERVED
SRCAINT
SRCBINT
SRCCINT
Rev. 0 | Page 74 of 296
Bit 4
JACKDECT
OCEP
LRPA
LRPB
LRPC
SRCA_
PBWRONG
SRCB_
PBWRONG
SRCC_
PBWRONG
DIN_CHAN0_
ADC_SWAP
DIN_CHAN1_
ADC_SWAP
DIN_CHAN2_
ADC_SWAP
DIN_CHAN3_
ADC_SWAP
DIN_CHAN4_
ADC_SWAP
DOUT_CHAN4_
AIFA_REC
DOUT_CHAN4_
AIFB_REC
DOUT_CHAN4_
AIFC_REC
DOUT_CHAN4_
DAC1
DOUT_CHAN4_
DAC2
DAIBRECVOLM
CLK1SDIV
CLK2SDIV
SRCARFRE_LOW
SRCBRFRE_LOW
SRCCRFRE_LOW
DAIARECLVOL
DAIARECRVOL
DAIAPBLVOL
DAIAPBRVOL
DAIBPBLVOL
DAIBPBRVOL
DAICPBLVOL
DAICPBRVOL
DEMPFS
Bit 3
MICB2OC
OCCDR
SRCAUNLOCK
SRCBUNLOCK
SRCCUNLOCK
DIN_CHAN0_ADC DIN_CHAN0_
DIN_CHAN1_ADC DIN_CHAN1_
DIN_CHAN2_ADC DIN_CHAN2_
DIN_CHAN3_ADC DIN_CHAN3_
DIN_CHAN4_ADC DIN_CHAN4_
DOUT_CHAN3_
AIFA_REC
DOUT_CHAN3_
AIFB_REC
DOUT_CHAN3_
AIFC_REC
DOUT_CHAN3_
DAC1
DOUT_CHAN3_
DAC2
DAIARECVOLM
CODECDRECVOLM CODECRECVOLM CODECPBBVOLM CODECPBAVOLM 0x00
DAIA_SR
DAIC_SR
DAIB_SR
WLA
WLB
WLC
Bit 2
MICB2THS
OCCDL
ADC_RESET_
FORCE
DEMPCEN
SRCAPBEN
SRCBPBEN
SRCCPBEN
AIFC_PB
AIFC_PB
AIFC_PB
AIFC_PB
AIFC_PB
DOUT_CHAN2_
AIFA_REC
DOUT_CHAN2_
AIFB_REC
DOUT_CHAN2_
AIFC_REC
DOUT_CHAN2_
DAC1
DOUT_CHAN2_
DAC2
DAICPBVOLM
CLK1ODIV
CLK2ODIV
SRCARFRE_HI
SRCBRFRE_HI
SRCCRFRE_HI
Bit 1
MICB1OC
OCHP
ADC_RESET
DEMPBEN
SRCARECEN
SRCBRECEN
SRCCRECEN
DIN_CHAN0_
AIFB_PB
DIN_CHAN1_
AIFB_PB
DIN_CHAN2_
AIFB_PB
DIN_CHAN3_
AIFB_PB
DIN_CHAN4_
AIFB_PB
DOUT_CHAN1_
AIFA_REC
DOUT_CHAN1_
AIFB_REC
DOUT_CHAN1_
AIFC_REC
DOUT_CHAN1_
DAC1
DOUT_CHAN1_
DAC2
DAIBPBVOLM
MCLK1DIV
MCLK2DIV
FORMATA
FORMATB
FORMATC
BPFA
BPFB
BPFC
Bit 0
MICB1THS
OT
PDETECT
DEMPAEN
DAIAEN
DAIBEN
DAICEN
DIN_CHAN0_
AIFA_PB
DIN_CHAN1_
AIFA_PB
DIN_CHAN2_
AIFA_PB
DIN_CHAN3_
AIFA_PB
DIN_CHAN4_
AIFA_PB
DOUT_CHAN0_
AIFA_REC
DOUT_CHAN0_
AIFB_REC
DOUT_CHAN0_
AIFC_REC
DOUT_CHAN0_
DAC1
DOUT_CHAN0_
DAC2
DAIAPBVOLM
Reset RW
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0A RW
0x0A RW
0x0A RW
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x08
0x08
0x08
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R
R
RW
MMRW
RW
MMRW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW