ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 147

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

CLK1_SOURCE_DIV REGISTER
Address: 0x40, Reset: 0x00, Name: CLK1_SOURCE_DIV
Clock 1 Divide and Core Clock Enable Control
Table 93. Bit Descriptions for CLK1_SOURCE_DIV
Bits
7
6
[5:3]
[2:0]
Bit Name
COREN
CLK1S_SEL
CLK1SDIV
MCLK1DIV
Settings
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0
1
0
1
Description
Core Clock Enable. Core clock enable or disable control.
Core clock disable (default)
Core clock enable
PLLA Bypass Signal. Clock source selection. Clock source can be set to
either PLLA output or external input.
Use PLLA clock as Source Clock 1 (default)
Use external clock as Source Clock 1
Source Clock 1 Divider. Source Clock 1 divider settings, 0 through 7 in
eight steps.
Source Clock Divider K = 0
Source Clock Divider K = 1
Source Clock Divider K = 2
Source Clock Divider K = 3
Source Clock Divider K = 4
Source Clock Divider K = 5
Source Clock Divider K = 6
Source Clock Divider K = 7
Master Clock 1 Divider. Master Clock 1 divider settings, 0 through 7 in
eight steps.
Divider J = 0
Divider J = 1
Divider J = 2
Divider J = 3
Divider J = 4
Divider J = 5
Divider J = 6
Divider J = 7
Rev. 0 | Page 147 of 296
Reset
0x0
0x0
0x0
0x0
ADAU1373
Access
RW
RW
RW
RW