ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 48

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

ADAU1373
Table 11, Table 12, and Table 13 also list the typical PLL settings
at 44.1 kHz and 48 kHz sample rates. Note that the PLL control
setting in hexadecimal format represents the 48 bits (six bytes)
for either PLLA or PLLB. For PLLA, the six bytes should be written
starting from Register 0x29 through Register 0x2E. For PLLB,
the six bytes should be written starting from Register 0x30
through Register 0x35.
PLL Lock Acquisition
The core clock for the device is disabled until the core clock enable
bit (Bit 7, COREN) in Register 0x40 is set to 1. It is recommended
that the audio outputs not be turned on until PLL lock is
established.
Table 11. Fractional PLL Parameter Settings for 44.1 kHz Base Sample Rate (PLL Output = 45.1584 MHz = 1024 × f
MCLK Input (MHz)
8
12
13
14.4
19.2
19.68
19.8
24
26
27
Table 12. Fractional PLL Parameter Settings for 48 kHz Base Sample Rate (PLL Output = 49.152 MHz = 1024 × f
MCLK Input (MHz)
8
12
13
14.4
19.2
19.68
19.8
24
26
27
Table 13. Integer PLL Parameter Settings for f
MCLK Input (MHz)
12.288
24.576
1
X = don’t care.
1
1
1
2
2
2
2
2
2
2
Input Divider (X)
Input Divider (X)
1
1
1
2
2
2
2
2
2
2
Input Divider (X)
1
1
S
Integer (R)
5
3
3
6
4
4
4
3
3
3
Integer (R)
6
4
3
6
5
4
4
4
3
3
Integer (R)
4
2
= 48 kHz (PLL Output = 49.152 MHz = 1024 × f
Rev. 0 | Page 48 of 296
Denominator (M)
625
625
8125
125
125
1025
1375
625
8125
1875
Denominator (M)
125
125
1625
75
25
205
825
125
1625
1125
Denominator (M)
Don’t care
Don’t care
To program the PLL during initialization or reconfiguration of
the clock setting, use the following procedure:
1.
2.
3.
4.
5.
6.
Bring the required blocks out of power-down (Register 0x25
to Register 0x27).
Ensure that the core clock is disabled (Register 0x40, Bit 7 = 0).
Enable the PLL (Register 0x2E, Bit 0, for PLLA; Register 0x35,
Bit 0, for PLLB).
Set the PLL control registers for the desired clock rate
(Register 0x28 to Register 0x2D for PLLA and Register 0x2F
to Register 0x34 for PLLB).
Poll the lock bit (Register 0x2E, Bit 2, and Register 0x35,
Bit 2, for APLL and Register 0x2E, Bit 3, and Register 0x35,
Bit 3, for DPLL). If the lock bit is set, proceed to Step 6;
otherwise, continue to poll. If no lock is established, check
the clock rate settings and clock to the device.
To ensure that the various blocks in the device are clocked
correctly, assert the core clock enable bit only after PLL
lock is acquired.
Numerator (N)
403
477
3849
34
88
604
772
477
3849
647
Numerator (N)
18
12
1269
62
3
204
796
12
1269
721
Numerator (N)
Don’t care
Don’t care
S
)
PLL Control Setting (Hex)
0x0271 0193 2901
0x0271 01DD 1901
0x1FBD 0F09 1901
0x007D 0022 3301
0x007D 0058 2301
0x0401 025C 2301
0x055F 0304 2301
0x0271 01DD 1B01
0x1FBD 0F09 1B01
0x0753 0287 1B01
PLL Control Setting (Hex)
0x007D 0012 3101
0x007D 000C 2101
0x0659 04F5 1901
0x004B 003E 3301
0x0019 0003 2B01
0x00CD 00CC 2301
0x0339 031C 2301
0x007D 000C 2301
0x0659 04F5 1B01
0x0465 02D1 1B01
PLL Control Setting (Hex)
0xXXXX XXXX 2001
0xXXXX XXXX 1001
S
)
S
)
1