ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 133

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

Bits
[3:0]
PLLA_CTRL1 REGISTER
Address: 0x29, Reset: 0x00, Name: PLLA_CTRL1
PLLA Fractional Mode Denominator M High Byte
Table 75. Bit Descriptions for PLLA_CTRL1
Bits
[7:0]
PLLA_CTRL2 REGISTER
Address: 0x2A, Reset: 0x00, Name: PLLA_CTRL2
PLLA Fractional Mode Denominator M Lower Byte
Table 76. Bit Descriptions for PLLA_CTRL2
Bits
[7:0]
Bit Name
DPLLA_NDIV
Bit Name
PLLA_M_HI
Bit Name
PLLA_M_LO
Settings
Settings
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1100
1101
1110
1111
1011
Description
DPLLA Clock Divider Setting. DPLLA clock divider settings from 1 to 1024
in 16 steps.
DPLLA output clock frequency: DPLLA input
DPLLA output clock frequency: DPLLA input clock frequency × 1024
DPLLA output clock frequency: DPLLA input clock frequency × 512
DPLLA output clock frequency: DPLLA input clock frequency × 256
DPLLA output clock frequency: DPLLA input clock frequency × 128
DPLLA output clock frequency: DPLLA input clock frequency × 64
DPLLA output clock frequency: DPLLA input clock frequency × 32
DPLLA output clock frequency: DPLLA input clock frequency × 16
DPLLA output clock frequency: DPLLA input clock frequency × 8
DPLLA output clock frequency: DPLLA input clock frequency × 4
DPLLA output clock frequency: DPLLA input clock frequency × 2
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Denominator (M) of the Fractional PLLA Upper Byte. PLLA Fractional Mode
Denominator M divider setting upper byte.
Description
Denominator (M) of the Fractional PLLA Lower Byte. PLLA Fractional Mode
Denominator M divider setting lower byte.
Rev. 0 | Page 133 of 296
Reset
0x0
Reset
0x00
Reset
0x00
ADAU1373
Access
RW
Access
RW
Access
RW