ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 46

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

ADAU1373
The PLL block consists of a digital PLL (DPLL), followed by an
analog PLL (APLL) with multiplexer. This architecture allows
flexibility in providing the clock to the ADAU1373. The DPLL
can accept clock rates from 8 kHz to 8 MHz and outputs clock
frequencies from 8 MHz to 27 MHz. The APLL can accept the
PLLA
PLLB
LRCLKA
LRCLKB
LRCLKC
LRCLKA
LRCLKB
LRCLKC
DIGITAL MIC 2 INPUT
DIGITAL MIC 1 INPUT
BCLKA
BCLKB
BCLKC
MCLK1
MCLK2
BCLKA
BCLKB
BCLKC
MCLK1
MCLK2
GPIO1
GPIO2
GPIO3
GPIO4
GPIO1
GPIO2
GPIO3
GPIO4
ANALOG IN MIXER
FS_A_EXT
BCLK_A
DOUT_A
DIN_A
FS_B_EXT
BCLK_B
DOUT_B
DIN_B
FS_C_EXT
BCLK_C
DOUT_C
DIN_C
OUTPUT MIXER
DPLLA_REF_SEL
DPLLB_REF_SEL
DMIC_CLK
EXTERNAL CLOCK > 8MHz
EXTERNAL CLOCK > 8MHz
REG. 0x28 DPLLA_CTRL
REG. 0x2F DPLLB_CTRL
INTERFACE A
INTERFACE B
INTERFACE C
DPLLA_NDIV
1....1024
IN 11 STEPS
8kHz TO 8MHz
DPLLB_NDIV
1....1024
IN 11 STEPS
8kHz TO 8MHz
DIGITAL
DIGITAL
DIGITAL
AUDIO
AUDIO
AUDIO
÷N
÷N
ADC
×1024
×1024
FS_A_INT
BCLK_A
DOUT_A
DIN_A
FS_B_INT
BCLK_B
DOUT_B
DIN_B
FS_C_INT
BCLK_C
DOUT_C
DIN_C
AIFCLK_A
AIFCLK_B
AIFCLK_A
AIFCLK_B
AIFCLK A
AIFCLK B
(256 × f
DMIC1
ADC/
DPLLA_CLK_OUT
DPLLB_CLK_OUT
DPLLA LOCK
INDICATOR
DPLLB LOCK
INDICATOR
S
DECIMATOR
DECIMATOR
)
DPLLA
DPLLB
ASRC_CLK (256 × f
DAC1
DAC2
ASRCA
ASRCB
ASRCC
DEC_CLK (128 × f
DEC_CLK (128 × f
DEC_CLK (128 × f
DEC_CLK (128 × f
FS_DSP
BCLK_DSP
DOUT_DSP
DIN_DSP
FS_DSP
BCLK_DSP
DOUT_DSP
DIN_DSP
FS_DSP
BCLK_DSP
DOUT_DSP
DIN_DSP
f
f
INB
INA
REG. 0x29 THROUGH REG. 0x2E PLLA CONTROL REGISTER
REG. 0x30 THROUGH REG. 0x35 PLLB CONTROL REGISTER
S
64 × f
)
S
X = 1 TO 4
X = 1 DEFAULT
X = 1 TO 4
X = 1 DEFAULT
S
S
S
S
)
)
)
)
÷ X
÷ X
ANALOG PLLA
ANALOG PLLB
DMIC2_DOUT
ADC/
DMIC1_DOUT
DAC1_PB
DAC2_PB
AIFA_REC
AIFA_PB
AIFB_REC
AIFB_PB
AIFC_REC
AIFC_PB
MIX/MUX
PLL
PLL
R = 0 TO 15
M AND N 16-BIT BINARY NUMBER
R = 2 DEFAULT
M = 253 DEFAULT
N = 0 DEFAULT
× (R + N/M)
R = 0 TO 15
M AND N 16-BIT BINARY NUMBER
R = 2 DEFAULT
M = 253 DEFAULT
N = 0 DEFAULT
× (R + N/M)
Figure 93. Clock Distribution
Rev. 0 | Page 46 of 296
(1024 × 48kHz)/(1024 × 44.1kHz)
(1024 × 48kHz)/(1024 × 44.1kHz)
CORE CLOCK ENABLE
EXTERNAL CLOCK
EXTERNAL CLOCK
APLLA CLOCK OUT
APLLB CLOCK OUT
FDSP_CH0_DOUT
FDSP_CH0_DIN
FDSP_CH1_DOUT
FDSP_CH1_DIN
FDSP_CH2_DOUT
FDSP_CH2_DIN
FDSP_CH3_DOUT
FDSP_CH3_DIN
FDSP_CH4_DOUT
FDSP_CH4_DIN
PLLA BYPASS
PLLB BYPASS
FDSP_CLK (128 × f
DSP
clock output from the DPLL and provide further fine resolution
to generate the clocks for internal blocks. If the input clock is
greater than 8 MHz, the DPLL can be powered down to save
power. In such a case, the external clock can be sent directly to
the APLL. See Figure 93 for a diagram of clock distribution
inside the ADAU1373.
S
)
CLK1 OUT
CLK2 OUT
3-BIT DIVIDER
3-BIT DIVIDER
CLK1_SOURCE_DIV (REG. 0x40)
CLK1SDIV
K = 0 TO 7
CLK2_SOURCE_DIV (REG. 0x42)
CLK2SDIV
K = 0 TO 7
÷ (K + 1)
÷ 1 TO 8
÷ (K + 1)
÷ 1 TO 8
3-BIT DIVIDER
3-BIT DIVIDER
MCLK1DIV
MCLK2DIV
J = 0 TO 7
J = 0 TO 7
÷ 1 TO 8
÷ 1 TO 8
÷ (J + 1)
÷ (J + 1)
CLK1_OUTPUT_DIV (REG. 0x41)
CLK2_OUTPUT_DIV (REG. 0x43)
5-BIT DIVIDER
5-BIT DIVIDER
P = 0 TO 31
P = 0 TO 31
CLK1ODIV
CLK2ODIV
44.1kHz × 256
44.1kHz × 256
÷ 1 TO 32
÷ 1 TO 32
48kHz × 256
32kHz × 256
÷ (P + 1)
÷ (P + 1)
32kHz × 256
48kHz × 256
256 ×
f
s
AIFCLKB
÷ 2
128 ×
128 ×
256 ×
f
f
f
s
s
s
MCLK2_OUT
MCLK1 OUT
ADC CLK/
DAC1/2 CLK
INT CLK/
DEC CLK/
FDSP CLK
ASRC CLK/
AIFCLKA