ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 151

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

CLK2_OUTPUT_DIV REGISTER
Address: 0x43, Reset: 0x00, Name: CLK2_OUTPUT_DIV
Master Clock 2 Output Divider Control for PLLB
Table 96. Bit Descriptions for CLK2_OUTPUT_DIV
Bits
[7:6]
5
[4:0]
Bit Name
RESERVED
CLK2OEN
CLK2ODIV
Settings
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
0
1
Description
Reserved.
CLK2 Output Enable. Output clock enable control.
CLK2 output disable (default)
CLK2 output enable
Output Clock 2 Divider. Output clock divider settings, 0 through 31.
Output Clock Divider P = 0
Output Clock Divider P = 1
Output Clock Divider P = 2
Output Clock Divider P = 3
Output Clock Divider P = 4
Output Clock Divider P = 5
Output Clock Divider P = 6
Output Clock Divider P = 7
Output Clock Divider P = 8
Output Clock Divider P = 9
Output Clock Divider P = 10
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Reset
0x0
0x0
0x00
ADAU1373
Access
RW
RW
RW