ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 69

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

INTERRUPT REQUEST (IRQ)
The ADAU1373 can generate an interrupt request based on
selected events from the various internal blocks. The interrupt
controller receives inputs from the MICBIAS current detect,
ASRC unlock detect, DRC signal activity detect, PLL unlock
detect, jack detect, and analog fault detect. Three registers are
provided for this function: Register 0xE5 can be used to set the
mask for the interrupts, Register 0xE6 stores the raw status
of the interrupts, and Register 0xE7 stores the status of the
interrupts after mask. The generation of interrupts can be
enabled or disabled using Register 0xE8, Bit 0.
The interrupts can be masked using the respective bits in
Register 0xE5. A bit setting of 1 unmasks the faults and generates
the interrupt request. The faults are reported in Register 0xE7.
When faults are unmasked, the status bits in Register 0xE7 are
latched until 1 is written to them. The raw status of the faults
can be read in Register 0xE6.
In addition, any of the above interrupts can be used to initiate the
IRQ (interrupt request) on the GPIOx pins. The four GPIO pins
can be set for IRQ function using Register 0xE3 and Register 0xE4.
The following events are reported in the interrupt status register
(Register 0xE6, IRQ_RAW):
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Unlocking of any of the three ASRCs. When either of the
three ASRC loses lock, the respective ASRCx_IRQ_RAW_
STATE bit is set.
The DRC input level exceeding the threshold set in
Register 0x8E, Register 0x9E, and Register 0xAE, which
sets the DRC_IRQ_RAW_STATE.
The on-chip PLL losing lock, which sets the PLL_UNLOCK_
RAW_STATE bit.
Any write to Register 0x36, Bits[1:0], which sets the
HP_CFG_RAW_STATE bit.
A change in the logic level at the JACKDET pin, which sets
the HP_DECT_RAW_STATE bit.
Occurrence of an analog fault, which sets the AFAULT_
RAW_STATE bit.
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The following analog faults can set the AFAULT_RAW_STATE bit:
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The overcurrent thresholds are fixed internally. The overtem-
perature fault is set when the die temperature exceeds 150°C ±
15°C.
The IRQs can be reported via GPIOx, or the IRQ_STATE register
(Register 0xE7) can be read via the I
is reporting a fault. The analog fault status in Register 0xE7 can be
used in conjunction with Register 0x39 or Register 0x38 to
differentiate among the analog faults.
Register 0x39 reports faults for an earpiece overcurrent, speaker
amplifier overcurrent, headphone amplifier overcurrent, and
die overtemperature.
In addition, Register 0x38 reports Microphone Bias 1 and Micro-
phone Bias 2 current detect, as well as overcurrent and logic
voltage changes at the JACKDET pin (Ball G5).
The MICB1THS and MICB2THS bits (Register 0x38, Bit 0 and
Bit 2, respectively) can be used to detect the connection of the
electret microphone at the MICBIASx pins (Ball C8 and Ball C9).
When the electrets microphone is connected, the current flow from
the MICBIASx pins to the microphone is detected. The current
detection threshold can be set using Register 0x22. Four settings
are provided: 150 μA (default), 330 μA, 510 μA, and 700 μA.
Similarly, the overcurrent at the MICBIASx outputs can be
detected. This allows for limiting the current drawn out of the
internal microphone bias regulator in case of a short circuit at
the MICBIASx pin. The overcurrent limit can be set to 330 μA,
700 μA, 1000 μA, or 1400 μA. The JACKDECT bit (Register 0x38,
Bit 4) can be used to detect the insertion/ removal of the accessory
at the headphone socket. When jack insertion is detected, the
status bit is set to 1.
The ADC/DAC clock loss is reported in Register 0x37.
Earpiece amplifier overcurrent
Speaker amplifier left channel overcurrent
Speaker amplifier right channel overcurrent
Headphone amplifier overcurrent or overtemperature
2
C to determine which block
ADAU1373