PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 96
PIC18F1230
Manufacturer Part Number
PIC18F1230
Description
18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F1230.pdf
(312 pages)
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PIC18F1230/1330
10.3
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of
peripheral interrupt sources, there are three Peripheral
Interrupt Enable registers (PIE1, PIE2 and PIE3). When
IPEN = 0, the PEIE bit must be set to enable any of
these peripheral interrupts.
REGISTER 10-7:
DS39758B-page 94
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
U-0
—
PIE Registers
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
RCIE: EUSART Receive Interrupt Enable bit
1 = Enables the EUSART receive interrupt
0 = Disables the EUSART receive interrupt
TXIE: EUSART Transmit Interrupt Enable bit
1 = Enables the EUSART transmit interrupt
0 = Disables the EUSART transmit interrupt
CMP2IE: Analog Comparator 2 Interrupt Enable bit
1 = Enables the CMP2 interrupt
0 = Disables the CMP2 interrupt
CMP1IE: Analog Comparator 1 Interrupt Enable bit
1 = The output of CMP1 has changed since last read
0 = The output of CMP1 has not changed since last read
CMP0IE: Analog Comparator 0 Interrupt Enable bit
1 = The output of CMP0 has changed since last read
0 = The output of CMP0 has not changed since last read
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
ADIE
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
W = Writable bit
‘1’ = Bit is set
RCIE
R-0
Advance Information
TXIE
R-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
CMP2IE
R/W-0
CMP1IE
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
CMP0IE
R/W-0
TMR1IE
R/W-0
bit 0
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