PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 307

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

SUBFWB .......................................................................... 243
SUBLW ............................................................................ 244
SUBULNK ........................................................................ 254
SUBWF ............................................................................ 244
SUBWFB .......................................................................... 245
SWAPF ............................................................................ 245
T
Table Reads/Table Writes ................................................. 48
TBLRD ............................................................................. 246
TBLWT ............................................................................. 247
Time-out in Various Situations (table) ................................ 37
Timer0 .............................................................................. 101
Timer1 .............................................................................. 105
Timing Diagrams
© 2006 Microchip Technology Inc.
16-Bit Mode Timer Reads and Writes ...................... 103
Associated Registers ............................................... 103
Clock Source Edge Select (T0SE Bit) ...................... 103
Clock Source Select (T0CS Bit) ............................... 103
Interrupt .................................................................... 103
Operation ................................................................. 103
Prescaler .................................................................. 103
Prescaler Assignment (PSA Bit) .............................. 103
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 103
Prescaler. See Prescaler, Timer0.
16-Bit Read/Write Mode ........................................... 108
Associated Registers ............................................... 109
Interrupt .................................................................... 108
Operation ................................................................. 106
Oscillator .......................................................... 105, 107
Oscillator Layout Considerations ............................. 107
Overflow Interrupt .................................................... 105
TMR1H Register ...................................................... 105
TMR1L Register ....................................................... 105
Use as a Clock Source ............................................ 107
Use as a Real-Time Clock ....................................... 108
A/D Conversion ........................................................ 286
Asynchronous Reception ......................................... 155
Asynchronous Transmission .................................... 152
Asynchronous Transmission (Back to Back) ........... 152
Automatic Baud Rate Calculation ............................ 150
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 156
BRG Overflow Sequence ......................................... 150
Brown-out Reset (BOR) ........................................... 282
CLKO and I/O .......................................................... 281
Clock/Instruction Cycle .............................................. 49
Dead-Time Insertion for Complementary PWM ....... 129
Duty Cycle Update Times in Continuous
Duty Cycle Update Times in Continuous
Edge-Aligned PWM .................................................. 126
EUSART Synchronous Receive
EUSART Synchronous Transmission
External Clock (All Modes Except PLL) ................... 279
Fail-Safe Clock Monitor ............................................ 199
Low-Voltage Detect Characteristics ......................... 276
Low-Voltage Detect Operation ................................. 182
Override Bits in Complementary Mode .................... 133
PWM Output Override Example #1 .......................... 135
PWM Output Override Example #2 .......................... 135
Switching the Assignment ................................ 103
Normal Operation ............................................ 156
Up/Down Count Mode ..................................... 126
Up/Down Count Mode with Double Updates ... 127
(Master/Slave) ................................................. 284
(Master/Slave) ................................................. 284
Advance Information
Timing Diagrams and Specifications ............................... 279
Top-of-Stack Access .......................................................... 46
TSTFSZ ........................................................................... 248
Two-Speed Start-up ................................................. 184, 197
Two-Word Instructions
TXSTA Register
PWM Period Buffer Updates in Continuous
PWM Period Buffer Updates in
PWM Time Base Interrupt
PWM Time Base Interrupt (Single-Shot Mode) ....... 121
PWM Time Base Interrupts (Continuous Up/Down
PWM Time Base Interrupts (Continuous
Reset, Watchdog Timer (WDT), Oscillator
Send Break Character Sequence ............................ 157
Slow Rise Time (MCLR Tied to V
Start of Center-Aligned PWM .................................. 127
Synchronous Reception
Synchronous Transmission ..................................... 158
Synchronous Transmission (Through TXEN) .......... 159
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 283
Transition for Entry to Idle Mode ............................... 30
Transition for Entry to SEC_RUN Mode .................... 27
Transition for Entry to Sleep Mode ............................ 29
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 30
Transition for Wake from Sleep (HSPLL) .................. 29
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 28
CLKO and I/O Requirements ................................... 281
EUSART Synchronous Receive
EUSART Synchronous Transmission
External Clock Requirements .................................. 279
PLL Clock ................................................................ 280
Reset, Watchdog Timer, Oscillator Start-up
Timer0 and Timer1 External Clock
Example Cases ......................................................... 50
BRGH Bit ................................................................. 145
Up/Down Count Modes ................................... 124
Free-Running Mode ......................................... 124
(Free-Running Mode) ...................................... 120
Count Mode with Double Updates) .................. 122
Up/Down Count Mode) .................................... 121
Start-up Timer (OST), Power-up
Timer (PWRT) ................................................. 282
V
(Master Mode, SREN) ..................................... 160
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 197
PRI_RUN Mode ................................................. 28
PRI_RUN Mode (HSPLL) .................................. 27
Requirements .................................................. 284
Requirements .................................................. 284
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 282
Requirements .................................................. 283
PIC18F1230/1330
DD
Rise > T
PWRT
DD
DD
) ............................................ 39
) .......................................... 39
, V
DD
DD
DD
, Case 1) ...................... 38
, Case 2) ...................... 38
Rise < T
DD
DS39758B-page 305
,
PWRT
) ........... 38