PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 241

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
After Instruction:
operation
Decode
PC = TOS
Q1
No
Return from Subroutine
RETURN {s}
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack is
popped and the top of the stack (TOS)
is loaded into the program counter. If
‘s’= 1, the contents of the shadow
registers, WS, STATUSS and BSRS,
are loaded into their corresponding
registers, W, STATUS and BSR. If
‘s’ = 0, no update of these registers
occurs (default).
1
2
operation
operation
RETURN
0000
Q2
No
No
[0,1]
W,
PC
BSR,
0000
operation
Process
STATUS,
Data
Q3
No
0001
from stack
Advance Information
operation
POP PC
Q4
No
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
PIC18F1230/1330
Q1
=
=
=
=
=
register ‘f’
(f<n>)
The contents of register ‘f’ are rotated
Rotate Left f through Carry
0
d
a
(f<7>)
(C)
C, N, Z
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is
selected. If ‘a’ is ‘1’, the BSR is used to
select the GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction
operates in Indexed Literal Offset
Addressing mode whenever
f
“Byte-Oriented and Bit-Oriented
Instructions in Indexed Literal Offset
Mode” for details.
1
1
RLCF
RLCF
Read
0011
Q2
95 (5Fh). See Section 21.2.3
1110 0110
0
1110 0110
1100 1100
1
f
[0,1]
[0,1]
dest<0>
255
C
dest<n + 1>,
C,
f {,d {,a}}
01da
Process
REG, 0, 0
Data
Q3
DS39758B-page 239
register f
ffff
destination
Write to
Q4
ffff