PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 136

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1230/1330
13.10.3
Figure 13-21 shows an example of a waveform that
might be generated using the PWM output override
feature. The figure shows a six-step commutation
sequence for a BLDC motor. The motor is driven
through a 3-phase inverter as shown in Figure 13-16.
When the appropriate rotor position is detected, the
PWM outputs are switched to the next commutation
state in the sequence. In this example, the PWM
outputs are driven to specific logic states. The
OVDCOND and OVDCONS register values used to
generate the signals in Figure 13-21 are given in
Table 13-4.
REGISTER 13-6:
REGISTER 13-7:
DS39758B-page 134
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
U-0
U-0
—
—
OUTPUT OVERRIDE EXAMPLES
Unimplemented: Read as ‘0’
POVD5:POVD0: PWM Output Override bits
1 = Output on PWM I/O pin is controlled by the value in the Duty Cycle register and the PWM time base
0 = Output on PWM I/O pin is controlled by the value in the corresponding POUTx bit
Unimplemented: Read as ‘0’
POUT5:POUT0: PWM Manual Output bits
1 = Output on PWM I/O pin is active when the corresponding PWM output override bit is cleared
0 = Output on PWM I/O pin is inactive when the corresponding PWM output override bit is cleared
U-0
U-0
—
—
OVDCOND: OUTPUT OVERRIDE CONTROL REGISTER
OVDCONS: OUTPUT STATE REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
POVD5
POUT5
R/W-1
R/W-0
Advance Information
POVD4
POUT4
R/W-1
R/W-0
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
POVD3
POUT3
R/W-1
R/W-0
The PWM Duty Cycle registers may be used in
conjunction with the OVDCOND and OVDCONS
registers. The Duty Cycle registers control the average
voltage across the load and the OVDCOND and
OVDCONS
sequence. Figure 13-22 shows the waveforms, while
Table 13-4 and Table 13-5 show the OVDCOND and
OVDCONS register values used to generate the
signals.
POVD2
POUT2
registers
R/W-1
R/W-0
© 2006 Microchip Technology Inc.
control
x = Bit is unknown
x = Bit is unknown
POVD1
POUT1
R/W-1
R/W-0
the
commutation
POVD0
POUT0
R/W-1
R/W-0
bit 0
bit 0