PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 84

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1230/1330
TABLE 9-1:
DS39758B-page 82
RA0/AN0/INT0/
KBI0/CMP0
RA1/AN1/INT1/
KBI1
RA2/TX/CK
RA3/RX/DT
RA4/T0CKI/AN2/
V
MCLR/V
FLTA
RA6/OSC2/CLKO/
T1OSO/T1CKI/AN3
RA7/OSC1/CLKI/
T1OSI/FLTA
Legend:
Note 1:
REF
+
2:
Pin
PP
/RA5/
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H.
Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.
PORTA I/O SUMMARY
T1OSO
Function
T1CKI
T1OSI
FLTA
FLTA
CMP0
T0CKI
V
MCLR
OSC2
CLKO
OSC1
INT0
KBI0
INT1
KBI1
CLKI
RA0
AN0
RA1
AN1
RA2
RA3
RA4
AN2
RA5
RA6
AN3
RA7
V
REF
TX
CK
RX
DT
PP
(1)
(1)
+
(2)
(2)
(2)
Setting
TRIS
0
1
1
1
1
1
0
1
1
1
1
0
1
0
0
1
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
1
1
0
1
1
1
1
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Advance Information
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
TTL
DIG
TTL
TTL
DIG
TTL
DIG
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
Analog input 0.
External interrupt 0.
Interrupt-on-change pin.
Comparator 0 input.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
Analog input 1.
External interrupt 1.
Interrupt-on-change pin.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
EUSART asynchronous transmit.
EUSART synchronous clock.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
EUSART asynchronous receive.
EUSART synchronous data.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 external clock input.
Analog input 2.
A/D reference voltage (high) input.
Master Clear (Reset) input. This pin is an active-low Reset to the device.
Programming voltage input.
Digital input.
Fault detect input for PWM.
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only.
Oscillator crystal output or external clock source output.
Oscillator crystal output.
Timer1 oscillator output.
Timer1 clock input.
Analog input 3.
LATA<7> data output. Disabled in external oscillator modes.
PORTA<7> data input. Disabled in external oscillator modes.
Oscillator crystal input or external clock source input.
External clock source input.
Timer1 oscillator input.
Fault detect input for PWM.
REF
output enabled.
REF
output enabled.
Description
© 2006 Microchip Technology Inc.