PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 78

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1230/1330
REGISTER 7-1:
DS39758B-page 76
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
EEPGD
R/W-x
When a WRERR occurs, the EEPGD or FREE bit is not cleared. This allows tracing of the error condition.
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
0 = Perform write-only
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: Erase/Write Enable bit
1 = Allows erase/write cycles
0 = Inhibits erase/write cycles
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle to is completed
RD: Read Control bit
1 = Initiates a memory read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be
0 = Read completed
R/W-x
CFGS
(cleared by completion of erase operation)
(MCLR or WDT Reset during self-timed erase or program operation)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)
set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)
EECON1: EEPROM CONTROL REGISTER 1
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U-0
—
Advance Information
R/W-0
FREE
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
(1)
WREN
R/W-0
© 2006 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0