PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 303

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

EUSART
Extended Instruction Set
External Clock Input ........................................................... 16
F
Fail-Safe Clock Monitor ............................................ 184, 198
Fast Register Stack ............................................................ 48
Firmware Instructions ....................................................... 208
Flash Program Memory ..................................................... 65
© 2006 Microchip Technology Inc.
Asynchronous Mode ................................................ 151
Baud Rate Generator
Baud Rate Generator (BRG) .................................... 145
Synchronous Master Mode ...................................... 158
Synchronous Slave Mode ........................................ 161
ADDFSR .................................................................. 251
ADDULNK ................................................................ 251
and Using MPLAB Tools .......................................... 257
CALLW ..................................................................... 252
Considerations for Use ............................................ 255
MOVSF .................................................................... 252
MOVSS .................................................................... 253
PUSHL ..................................................................... 253
SUBFSR .................................................................. 254
SUBULNK ................................................................ 254
Syntax ...................................................................... 250
Exiting Operation ..................................................... 198
Interrupts in Power-Managed Modes ....................... 199
POR or Wake from Sleep ........................................ 199
WDT During Oscillator Failure ................................. 198
Associated Registers ................................................. 73
Control Registers ....................................................... 66
Erase Sequence ........................................................ 70
Erasing ....................................................................... 70
Operation During Code-Protect ................................. 73
Reading ...................................................................... 69
Table Pointer
12-Bit Break Character Sequence ................... 157
Associated Registers, Receive ........................ 155
Associated Registers, Transmit ....................... 153
Auto-Wake-up on Sync Break Character ......... 155
Receiver ........................................................... 154
Receiving a Break Character ........................... 157
Setting Up 9-Bit Mode with
Transmitter ....................................................... 151
Operation in Power-Managed Modes .............. 145
Associated Registers ....................................... 146
Auto-Baud Rate Detect .................................... 149
Baud Rate Error, Calculating ........................... 146
Baud Rates, Asynchronous Modes ................. 147
High Baud Rate Select (BRGH Bit) ................. 145
Sampling .......................................................... 145
Associated Registers, Receive ........................ 160
Associated Registers, Transmit ....................... 159
Reception ......................................................... 160
Transmission ................................................... 158
Associated Registers, Receive ........................ 162
Associated Registers, Transmit ....................... 161
Reception ......................................................... 162
Transmission ................................................... 161
EECON1 and EECON2 ..................................... 66
TABLAT (Table Latch) Register ......................... 68
TBLPTR (Table Pointer) Register ...................... 68
Boundaries Based on Operation ........................ 68
Operations with TBLRD
Address Detect ........................................ 154
and TBLWT (table) .................................... 68
Advance Information
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 229
H
Hardware Multiplier ............................................................ 79
I
I/O Ports ............................................................................ 81
ID Locations ............................................................. 184, 203
INCF ................................................................................ 229
INCFSZ ............................................................................ 230
In-Circuit Debugger .......................................................... 203
In-Circuit Serial Programming (ICSP) ...................... 184, 203
Independent PWM Mode
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 255
Indirect Addressing ............................................................ 60
INFSNZ ............................................................................ 230
Initialization Conditions for all Registers ...................... 41–44
Instruction Cycle ................................................................ 49
Instruction Set .................................................................. 208
Table Pointer Boundaries .......................................... 68
Table Reads and Table Writes .................................. 65
Write Sequence ......................................................... 71
Writing ....................................................................... 71
Introduction ................................................................ 79
Operation ................................................................... 79
Performance Comparison .......................................... 79
Duty Cycle Assignment ........................................... 131
Output ...................................................................... 131
Output, Channel Override ........................................ 132
and Standard PIC18 Instructions ............................. 255
Clocking Scheme ....................................................... 49
Flow/Pipelining .......................................................... 49
ADDLW .................................................................... 214
ADDWF ................................................................... 214
ADDWF (Indexed Literal Offset Mode) .................... 256
ADDWFC ................................................................. 215
ANDLW .................................................................... 215
ANDWF ................................................................... 216
BC ............................................................................ 216
BCF ......................................................................... 217
BN ............................................................................ 217
BNC ......................................................................... 218
BNN ......................................................................... 218
BNOV ...................................................................... 219
BNZ ......................................................................... 219
BOV ......................................................................... 222
BRA ......................................................................... 220
BSF .......................................................................... 220
BSF (Indexed Literal Offset Mode) .......................... 256
BTFSC ..................................................................... 221
BTFSS ..................................................................... 221
BTG ......................................................................... 222
BZ ............................................................................ 223
CALL ........................................................................ 223
CLRF ....................................................................... 224
CLRWDT ................................................................. 224
COMF ...................................................................... 225
CPFSEQ .................................................................. 225
CPFSGT .................................................................. 226
Protection Against Spurious Writes ................... 73
Unexpected Termination ................................... 73
Write Verify ........................................................ 73
PIC18F1230/1330
DS39758B-page 301