PIC18F1230 MICROCHIP [Microchip Technology], PIC18F1230 Datasheet - Page 59

• Manufacturer Part Number: PIC18F1230
• Description: 18/20/28-Pin, Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 5-2:
© 2006 Microchip Technology Inc.
PTMRL
PTMRH
PTPERL
PTPERH
TRISB
TRISA
PDC0L
PDC0H
PDC1L
PDC1H
PDC2L
PDC2H
FLTCONFIG
LATB
LATA
SEVTCMPL
SEVTCMPH
PWMCON0
PWMCON1
DTCON
OVDCOND
OVDCONS
PORTB
PORTA
Legend:
Note 1:
File Name
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and
reads as ‘0’. See Section 4.4 “Brown-out Reset (BOR)”.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See
Section 2.6.4 “PLL in INTOSC Modes”.
The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads
as ‘0’. This bit is read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
Bit 7 and bit 6 are cleared by user software or by a POR.
Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
This bit has no effect if the Configuration bit, WDTEN, is enabled.
PWM Time Base Register (lower 8 bits)
PWM Time Base Period Register (lower 8 bits)
PORTB Data Direction Control Register
PWM Duty Cycle #0L Register (lower 8 bits)
PWM Duty Cycle #1L Register (lower 8 bits)
PWM Duty Cycle #2L Register (lower 8 bits)
PORTB Data Latch Register (Read and Write to Data Latch)
PWM Special Event Compare Register (lower 8 bits)
SEVOPS3
TRISA7
LATA7
BRFEN
DTPS1
RA7
Bit 7
RB7
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)
(4)
(4)
(4)
PWMEN2
SEVOPS2
TRISA6
LATA6
DTPS0
RA6
Bit 6
RB6
—
—
—
—
—
—
—
—
—
(4)
(4)
(4)
(6)
PORTA Data Direction Control Register
PWM Duty Cycle #0H Register (upper 6 bits)
PWM Duty Cycle #1H Register (upper 6 bits)
PWM Duty Cycle #2H Register (upper 6 bits)
PORTA Data Latch Register (Read and Write to Data Latch)
PWMEN1
SEVOPS1
POVD5
POUT5
RA5
Bit 5
DT5
RB5
—
—
—
—
(3)
(6)
Advance Information
PWMEN0
SEVOPS0
POVD4
POUT4
Bit 4
DT4
RB4
RA4
—
—
—
—
(6)
PWM Time Base Register (upper 4 bits)
PWM Time Base Period Register (upper 4 bits)
PWM Special Event Compare Register (upper 4 bits)
SEVTDIR
POVD3
POUT3
Bit 3
RB3
RA3
DT3
—
—
PMOD2
POVD2
POUT2
FLTAS
Bit 2
DT2
RB2
RA2
—
PIC18F1230/1330
FLTAMOD
PMOD1
POVD1
POUT1
UDIS
Bit 1
RB1
RA1
DT1
FLTAEN
PMOD0
OSYNC
POVD0
POUT0
Bit 0
DT0
RB0
RA0
DS39758B-page 57
0000 0000 43, 119
---- 0000 43, 119
1111 1111 43, 119
---- 1111 43, 119
1111 1111 43, 84
1111 1111 43, 81
0000 0000 43, 125
--00 0000 43, 125
0000 0000 43, 125
--00 0000 43, 125
0000 0000 43, 125
--00 0000 43, 125
0--- -000 43, 137
xxxx xxxx 43, 84
xxxx xxxx 43, 81
0000 0000 43, 138
---- 0000 44, 138
-100 -000 44, 117
-000 -000
0000 0-00 44, 118
0000 0000 44, 130
--11 1111 44, 134
--00 0000 44, 134
xxxx xxxx 44, 84
xx0x xxxx 44, 81
POR, BOR
Value on
Details
page:
on