DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 96

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

PMID
PMID
RXC OUT
RXC OUT
RXD OUT
RXD OUT
RXC IN
RXC IN
RXD IN
RXD IN
PMRD
PMRD
TXC
TXC
SD
SD
6 0 Signal Descriptions
Alternate PMD Interface
Symbol
a
b
b
a
a
b
a
b
a
b
a
b
a
b
a
b
Pin
42
41
36
35
52
51
48
47
50
49
34
33
31
30
40
39
I O
O
O
O
O
I
I
I
I
PMD Indicate Data Differential 100k ECL 125 Mbps serial data input signals from the PMD
Receiver into the Clock Recovery Module (CRM) of the PLAYER
Recovered Clock Out 125 MHz clock recovered by the Clock Recovery Module (CRM) from the
PMID data input
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used they should be left Not Connected (N C)
Recovered Data Out 125 Mbps data recovered by the Clock Recovery Module (CRM) from the
PMID data input
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used they should be left Not Connected (N C)
Receive Clock In Clock inputs to the Player section of the PLAYER
synchronized with the RXD IN inputs
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used pin 76 should be left Not Connected (N C) and pin 75 should be
connected directly to ground (Reserved 0)
Receive Data In Data inputs to the Player section of the PLAYER
synchronized with the RXC IN inputs
These signals are only active when the Alternate PMD Enable (APMDEN) bit of the Alternate PMD
Register (APMDREG) is set to a 1 and are off by default after Reset
When these two pins are not used pin 78 should be left Not Connected (N C) and pin 77 should be
connected directly to ground (Reserved 0)
PMD Request Data Differential 100k ECL 125 Mbps serial data output signals to the PMD
transmitter
Transmit Clock 125 MHz 100k ECL compatible differential outputs synchronized to the outgoing
PMRD data
These signals can be enabled using the Transmit Clock Enable (TXCE) bit in the Clock Generation
Module Register (CGMREG)
When these two pins are not used they should be left Not Connected (N C)
Signal Detect Differential 100k ECL input signals from the PMD receiver indicating that a signal
is being received by the PMD receiver
(Continued)
96
Description
a
a
a
These inputs must be
These inputs must be