DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 72

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 28 CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR)
The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER
device before it can be written to by the Control Bus Interface
The current state of the Current Transmit State Register (CTSR) is automatically written into the Current Transmit State
Comparison Register A (i e CTSCR
During a Control Bus Interface write cycle the PLAYER
Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within the CTSR when the value of a bit in the CTSR
differs from the value of the corresponding bit in the Current Transmit State Comparison Register
ACCESS RULES
RESC
TM0C
TM1C
TM2C
IC0C
IC1C
SEC
PRDPEC
RESC
Symbol
D7
ADDRESS
1Bh
PRDPEC
TRANSMIT MODE
Current Transmit State Register (CTSR)
TRANSMIT MODE
Current Transmit State Register (CTSR)
TRANSMIT MODE
Current Transmit State Register (CTSR)
INJECTION CONTROL
Current Transmit State Register (CTSR)
INJECTION CONTROL
Current Transmit State Register (CTSR)
SMOOTHER ENABLE COMPARISON The comparison bit for the Smoother Enable bit (SE) of the Current
Transmit State Register (CTSR)
PHY REQUEST DATA PARITY ENABLE COMPARISON The comparison bit for the PHY Request Data
Parity Enable bit (PRDPE) of the Current Transmit State Register (CTSR)
RESERVED COMPARISON The comparison bit for the Reserved bit (RES) of the Current Transmit State
Register (CTSR)
D6
(Continued)
Always
READ
SEC
D5
k
k
k
e
0
1
2
CTSR) during a Control Bus Interface read cycle of CTSR
l
l
l
k
k
COMPARISON The comparison bit for the Transmit Mode
COMPARISON The comparison bit for the Transmit Mode
COMPARISON The comparison bit for the Transmit Mode
0
1
l
l
IC1C
COMPARISON The comparison bit for the Injection Control
COMPARISON The comparison bit for the Injection Control
WRITE
D4
Always
a
IC0C
device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
D3
72
Description
TM2C
D2
TM1C
D1
TM0C
D0
k
k
k
0
1
2
l
l
l
bit (TM0) of the
bit (TM1) of the
bit (TM2) of the
k
k
0
1
l
l
bit (IC0) of the
bit (IC1) of the
a