DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 47

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 4 INTERRUPT CONDITION MASK REGISTER (ICMR)
The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt
The Interrupt pin will be asserted (i e E INT
to 1 and the corresponding mask bits in this register are also set to 1
This register is cleared (i e set to 0) and all interrupts are initially masked during the reset process
ACCESS RULES
UDIM
Symbol
DPEM
CPEM
CCRM
CWIM
LEMTM
RCAM
RCBM
UDIM
D7
ADDRESS
03h
PHY REQUEST DATA PARITY ERROR MASK The mask bit for the PHY Request Data Parity Error bit
(DPE) of the Interrupt Condition Register (ICR)
Control Bus DATA PARITY ERROR MASK The mask bit for the Control Bus Data Parity Error bit (CPE) of the
Interrupt Condition Register (ICR)
Control Bus WRITE COMMAND REJECT MASK The mask bit for the Control Bus Write Command Reject bit
(CCR) of the Interrupt Condition Register (ICR)
CONDITIONAL WRITE INHIBIT MASK The mask bit for the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR)
LINK ERROR MONITOR THRESHOLD MASK The mask bit for the Link Error Monitor Threshold bit (LEMT) of
the Interrupt Condition Register (ICR)
RECEIVE CONDITION A MASK The mask bit for the Receive Condition A bit (RCA) of the Interrupt Condition
Register (ICR)
RECEIVE CONDITION B MASK The mask bit for the Receive Condition B bit (RCB) of the Interrupt Condition
Register (ICR)
USER DEFINABLE INTERRUPT MASK The mask bit for the User Definable Interrupt bit (UDI) of the Interrupt
Condition Register (ICR)
RCBM
D6
(Continued)
Always
READ
RCAM
D5
LEMTM
e
D4
WRITE
GND) when one or more bits within the Interrupt Condition Register (ICR) are set
Always
CWIM
D3
47
Description
CCRM
D2
CPEM
D1
DPEM
D0