DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 100

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

Symbol
EP0
EP1
E RST
6 0 Signal Descriptions
MISCELLANEOUS INTERFACE
The Miscellaneous Interface consist of a reset signal and user definable enable signals
Pin
71
41
43
I O
O
O
I
Reset An active low TTL input signal which clears all registers The signal must be kept asserted for a
minimum amount of time Once the E RST signal is asserted the PLAYER
the specified amount of time to reset internal logic Note that bit zero of the Mode Register will be set to
zero (i e Stop Mode) See section 4 2 Stop Mode of Operation for more information
User Definable Enable Pin 0 A TTL output signal allowing control of external logic through the Control
Bus Interface EP0 is asserted deasserted through Enable Bit 0 (EB0) of the User Definable Register
(UDR) When Enable Bit 0 is set to zero EP0 is deasserted When Enable Bit 0 is set to one EP0 is
asserted
User Definable Enable Pin 1 A TTL output signal allowing control of external logic through the Control
Bus Interface EP1 is asserted deasserted through Enable Bit 1 (EB1) of the User Definable Register
(UDR) When Enable Bit 1 is set to zero EP1 is deasserted When Enable Bit 1 is set to one EP1 is
asserted
(Continued)
100
Description
a
device should be allowed