DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 63
DP83256VF-AP
Manufacturer Part Number
DP83256VF-AP
Description
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83256VF-AP.pdf
(144 pages)
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D0 –D7
5 0 Registers
5 19 STATE PRESCALE THRESHOLD REGISTER (SPTR)
The State Prescale Threshold Register contains the start value for the State Prescale Timer The State Prescale Timer is a down
counter It is used in conjunction with the State Timer to count the Line State duration
The threshold values for the State Timer and State Prescale Timer are simultaneously loaded into both timers if one of the
following conditions is true
1 Both the State Timer and State Prescale Timer reach zero and the current Line State is Halt Line State Idle Line State
or
2 A Line State change occurs and the new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or
or
3 The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle
The State Prescale Timer will decrement every 80 ns if the current Line State is Halt Line State Idle Line State Master Line
State Quiet Line State or No Signal Detect
ACCESS RULES
Bit
Master Line State Quiet Line State or No Signal Detect
No Signal Detect
SPT7
D7
ADDRESS
SPT0–SPT7
12h
Symbol
SPT6
D6
(Continued)
STATE PRESCALE THRESHOLD BIT
SPT0 is the Least Significant Bit (LSB)
Always
READ
SPT5
D5
SPT4
D4
WRITE
Always
SPT3
D3
63
k
0 –7
l
Description
SPT2
Start value for the State Prescale Timer
D2
SPT1
D1
SPT0
D0
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