DP83256VF-AP NSC [National Semiconductor], DP83256VF-AP Datasheet - Page 58

• Manufacturer Part Number: DP83256VF-AP
• Manufacturer: NSC [National Semiconductor]

D0-D6
D7
5 0 Registers
5 14 NOISE THRESHOLD REGISTER (NTR)
The Noise Threshold Register contains the start value for the Noise Timer This threshold register is used in conjunction with the
Noise Prescale Threshold register for setting the maximum allowable time between entry to ILS HLS MLS ALS or NSD line
states The Noise timer is used to implement the TNE timing requirement of PCM The Noise timer decrements by one for every
80 x (NPTR
zero
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true
1 Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State Active
or
2 The current Line State is either Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect
or
3 The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle
In addition the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero
The Noise Counter and Noise Prescale Counter will continue to count without resetting or reloading the threshold values if a
Line State change occurs and the new line state is either Noise Line State Active Line State or Line State Unknown
When both the Noise Threshold Counter and Noise Counter both reach zero the Noise Threshold bit of the Receive Condition
Register A will be set
The recommended default value for the NTR register is 40h and for the NPTR register is F9h which corresponds to 1 3 ms as
specified in the ANSI standard
ACCESS RULES
Bit
Line State or Line State Unknown
RES
D7
ADDRESS
NT0-NT6
RES
Symbol
0Dh
a
1) ns in case of Noise events As a result the internal noise counter takes the following amount of time to reach
NT6
D6
NOISE THRESHOLD BIT
NT0 is the Least Significant Bit (LSB)
RESERVED Reserved for future use
Note Users are discouraged from using this bit Write data is ignored since the reserved bit is permanently set to 0
(Continued)
Always
READ
NT5
D5
NT4
((NPTR
k
D4
WRITE
Always
0-6
l
a
Start value for the Noise Counter
1) x NTR
NT3
D3
58
a
NPTR) x 80 ns
Description
NT2
D2
NT1
D1
NT0
D0